Device having data sharing capabilities and a method for sharing data
View Patent ↗A method and device for sharing data. The method include: receiving, by a direct memory access controller, a data read instruction; wherein the read data instruction can be a shared data read instruction or a non-shared data read instruction; determining whether to fetch a requested data block from a first memory unit to a second memory unit by applying a direct memory address control operation; wherein the second memory unit is accessible by a processor that generated the shared data read instruction; fetching the requested data block from the first memory unit to the second memory unit by applying a direct memory access control operation, if the read data instruction is a non-shared data instruction or if the read data instruction is a shared data instruction but the requested data is not stored in the second memory unit; and retrieving a requested data block from a second memory unit.
1. A method comprising:
receiving, by a direct memory access controller, a first shared data read instruction;
determining whether to fetch a first requested data block from a first memory unit to a second memory unit, wherein the second memory unit is accessible by a processor that generated the shared data read instruction, and wherein the determining includes determining whether a first source address included in the first shared data read instruction is included in a shared data physical address array of the direct memory access controller; and
in response to determining that the first source address is not included in the shared data physical address array:
fetching the first requested data block from the first memory unit to the source address;
storing the first requested data block at a first physical address in the second memory unit:
storing a first pointer at a second physical address in the second memory unit, wherein the first pointer is to the first physical address and the second physical address is associated with a first destination address included in the first shared data read instruction; and
storing the first source address in the shared data physical address array.
2. A device comprising:
a first memory unit and at least one processor configured to access a second memory unit; and
a direct memory access controller that is configured to:
receive a first shared data read instruction
determine whether to fetch a first requested data block from the first memory unit to the second memory unit, wherein the determining includes determining whether a first source address included in the first shared data read instruction is included in a shared data physical address array of the direct memory access controller; and
in response to determining that the first source address is not included in the shared data physical address array, to:
(iii) fetch the first requested data block from the first memory unit to the source address;
store the first requested data block at a first physical address in the second memory unit;
store a first pointer at a second physical address in the second memory unit, wherein the first pointer is to the first physical address and the second physical address is associated with a first destination address included in the first shared data read instruction; and
store the first source address in the shared data physical address array.
3. The method of claim 1 , wherein:
in further response to determining that the first source address is not included in the shared data physical address array, the method comprises storing a count in a counter array of the direct memory access controller, wherein the count is associated with the first source address.
4. The method of claim 3 , wherein
in further response to determining that the first source address is not included in the shared data physical address array, the method comprises initializing a watchdog counter associated with the first source address.
5. The method of claim 4 , further comprising:
decrementing the count in response to the watchdog counter counting a time window.
6. The method of claim 3 , further comprising:
receiving by the direct memory access controller a second shared data read instruction;
determining that a second source address included in the second shared data read instruction is the same as the first source address; and
in response to determining that the second source address is the same as the first source address:
storing a second pointer at a third physical address in the second memory unit, wherein the second pointer is to the first physical address and the third physical address is associated with a second destination address included in the second shared data read instruction; and
incrementing the count.
7. The method of claim 6 , further comprising:
receiving by the direct memory access controller a shared data write instruction;
determining that a third source address included in the shared data write instruction is the same as the first source address; and
in response to determining that the third source address is the same as the first source address, decrementing the count.
8. The method of claim 1 , further comprising:
in response to determining that the first source address is included in the shared data physical address array, storing a second pointer at a third physical address in the second memory unit, wherein the second pointer is to the first physical address and the third physical address is associated with the first destination address.
9. The method of claim 8 , wherein:
in further response to determining that the first source address is included in the shared data physical address array, the method comprises incrementing a count in a counter array of the direct memory access controller, wherein the count is changed based upon accesses to the first source address.
10. The device of claim 2 , wherein:
in further response to determining that the first source address is not included in the shared data physical address array, the direct memory access controller is further configured to store a count in a counter array of the direct memory access controller, wherein the count is associated with the first source address.
11. The device of claim 10 , wherein
in further response to determining that the first source address is not included in the shared data physical address array, the direct memory access controller is further configured to initialize a watchdog counter associated with the first source address.
12. The device of claim 11 , wherein:
the direct memory access controller is further configured to decrement the count in response to the watchdog counter counting a time window.
13. The device of claim 10 , wherein the direct memory access controller is further configured to:
receive from the processor a second shared data read instruction;
determine that a second source address included in the second shared data read instruction is the same as the first source address; and
in response to determining that the second source address is the same as the first source address:
store a second pointer at a third physical address in the second memory unit, wherein the second pointer is to the first physical address and the third physical address is associated with a second destination address included in the second shared data read instruction; and
increment the count.
14. The device of claim 13 , wherein the direct memory access controller is further configured to:
receive by the direct memory access controller a shared data write instruction;
determine that a third source address included in the shared data write instruction is the same as the first source address; and
in response to determining that the third source address is the same as the first source address, decrement the count.
15. The device of claim 2 , wherein:
in response to determining that the first source address is included in the shared data physical address array, the direct memory access controller is further configured to store a second pointer at a third physical address in the second memory unit, wherein the second pointer is to the first physical address and the third physical address is associated with the first destination address.
16. The device of claim 15 , wherein:
in further response to determining that the first source address is included in the shared data physical address array, the direct memory access controller is further configured to increment a count in a counter array of the direct memory access controller, wherein the count is changed based upon accesses to first source address.
17. A direct memory access controller comprising a controller configured to:
receive from the processor an instruction;
determine that the instruction is a shared data instruction based upon a shared data field of the instruction;
if the instruction is a shared data instruction, fetch a data block stored at a location in a first memory unit that is designated by a source field of the instruction and store the data block in a second memory unit at a first location in the second memory unit that is reserved for shared data; and
if the instruction is not a shared data instruction, fetch the data block and store the data block in the second memory unit at a second location in the second memory unit that is reserved for non-shared data, wherein the second location is designated by a destination field of the instruction;
wherein, if the instruction is a shared data instruction, the controller is further configured to store a pointer to the first location at a third location in the second memory unit, wherein the third location is designated by the destination field; and if the instruction is a shared data instruction, the controller is further configured to store the source field in an address array of the direct memory access controller.
18. The direct memory access controller of claim 17 , wherein, if the instruction is a shared data instruction, the controller is further configured to initialize a watchdog counter.