Reference potential generating circuit of semiconductor memory
There is provided a reference potential generating circuit of a semiconductor memory, including: a first MOS transistor group that includes a plurality of first MOS transistors that are connected in series; a second MOS transistor that is connected in series to the first MOS transistor group; a third MOS transistor that is connected in parallel to the circuit in which the first MOS transistor group and the second MOS transistor are connected in series, has a gate connected to a connection point of the first MOS transistor group and the second MOS transistor, and corrects a reference potential from a connection point of the first MOS transistors; and a fourth MOS transistor that is connected to the gate of the third MOS transistor, and decreases the potential of the gate of the third MOS transistor when a permission signal to supply power to the semiconductor memory is input.
1. A reference potential generating circuit of a semiconductor memory, comprising:
a first MOS transistor group that includes a plurality of first MOS transistors, which are used for supply of current to an internal circuit of the semiconductor memory and are connected in series;
a second MOS transistor that is connected in series to the first MOS transistor group and is used for temperature compensation;
a third MOS transistor that is connected to a circuit in which the first MOS transistor group and the second MOS transistor are connected in series, has a gate connected to a connection point of the first MOS transistor group and the second MOS transistor, and corrects a reference potential output from a predetermined connection point of the plurality of first MOS transistors; and
a fourth MOS transistor that is connected to the gate of the third MOS transistor, and decreases the potential of the gate of the third MOS transistor when a permission signal to permit the supply of current to the internal circuit of the semiconductor memory is input.
2. The reference potential generating circuit of a semiconductor memory of claim 1 , wherein the fourth MOS transistor is an NMOS transistor of which a drain and a source are connected to the gate of the third MOS transistor and, of which a gate receives the permission signal.
3. The reference potential generating circuit of a semiconductor memory of claim 1 , wherein the fourth MOS transistor is a PMOS transistor of which a gate is connected to the third MOS transistor and, of which a drain and a source receive the permission signal.
4. The reference potential generating circuit of a semiconductor memory of claim 1 , wherein inverters of an even number are provided between the fourth MOS transistor and terminals receiving the permission signal.