Memory access device including multiple processors
View Patent ↗Provided is a memory access device including multiple processors accessing a specific memory. The memory access device includes first and second processors, first and second transaction controllers, a memory access switch, and a memory controller. The first and second transaction controllers are connected respectively to the first and second processors. The memory access switch is connected to the first and second transaction controllers. The memory controller is connected to the memory access switch to control a memory device. Herein, if the first and second processors simultaneously access the memory device, the second processor stores an address or data in the second transaction controller while the first processor is accessing the memory device.
1. A memory access device comprising:
first and second processors;
first and second transaction controllers coupled respectively to the first and second processors;
a memory access switch coupled to the first and second transaction controllers; and
a memory controller coupled to the memory access switch to control a memory device,
wherein if the first and second processors simultaneously access the memory device, the second processor is configured to store an address or data in the second transaction controller while the first processor is accessing the memory device, and
wherein the memory access switch comprises a bandwidth control scheduler configured to store schedule information about the access of the memory device by the first and second processors, and wherein the bandwidth control scheduler is configured to transmit the stored schedule information to the first and second transaction controllers.
2. The memory access device of claim 1 , wherein the stored schedule information is transmitted from an external device by a user.
3. The memory access device of claim 1 , wherein the memory access switch comprises a bus matrix.
4. The memory access device of claim 1 , wherein the first transaction controller comprises:
a data buffer configured to store data temporarily;
an address table configured to store an address corresponding to the data stored in the data buffer;
an address comparator configured to compare the address stored in the address table and an address requested by the first processor and output a comparison result; and
a stream controller configured to receive the comparison result from the address comparator and connect the first processor and the memory access switch according to the received comparison result.
5. The memory access device of claim 4 , wherein if the address requested by the first processor is included in the address table, the stream controller outputs data, corresponding to the address requested by the first processor, from the data buffer to the first processor.
6. The memory access device of claim 4 , wherein if the address requested by the first processor is not included in the address table, the stream controller outputs data, corresponding to the address requested by the first processor, from the memory device to the first processor.
7. The memory access device of claim 1 , wherein the second transaction controller comprises:
a data buffer configured to store data temporarily;
an address table configured to store an address corresponding to the data stored in the data buffer;
an address comparator configured to compare the address stored in the address table and an address requested by the second processor and output a comparison result; and
a stream controller configured to receive the comparison result from the address comparator and connect the second processor and the memory access switch according to the received comparison result.
8. The memory access device of claim 7 , wherein if the address requested by the second processor is included in the address table, the stream controller outputs data, corresponding to the address requested by the second processor, from the data buffer to the second processor.
9. The memory access device of claim 7 , wherein if the address requested by the second processor is not included in the address table, the stream controller outputs data, corresponding to the address requested by the second processor, from the memory device to the second processor.
10. A memory access device comprising:
first and second processors;
first and second transaction controllers coupled respectively to the first and second processors;
a memory access switch coupled to the first and second transaction controllers; and
a memory controller coupled to the memory access switch to control a memory device,
wherein if the first and second processors simultaneously access the memory device, the second processor is configured to store an address or data in the second transaction controller while the first processor is accessing the memory device, and
wherein the first transaction controller comprises:
a data buffer configured to store data temporarily;
an address table configured to store an address corresponding to data stored in the data buffer;
an address comparator configured to compare the address stored in the address table and an address requested by the first processor and output a comparison result; and
a stream controller configured to receive the comparison result from the address comparator and connect the first processor and the memory access switch according to the received comparison result.
11. The memory access device of claim 10 , wherein if the address requested by the first processor is included in the address table, the stream controller is configured to output data, corresponding to the address requested by the first processor, from the data buffer to the first processor.
12. The memory access device of claim 10 , wherein if the address requested by the first processor is not included in the address table, the stream controller is configured to output data, corresponding to the address requested by the first processor, from the memory device to the first processor.
13. A memory access device comprising:
first and second processors;
first and second transaction controllers coupled respectively to the first and second processors;
a memory access switch coupled to the first and second transaction controllers; and
a memory controller coupled to the memory access switch to control a memory device,
wherein if the first and second processors simultaneously access the memory device, the second processor stores an address or data in the second transaction controller while the first processor is accessing the memory device, and
wherein the second transaction controller comprises:
a data buffer configured to store data temporarily;
an address table configured to store an address corresponding to data stored in the data buffer;
an address comparator configured to compare the address stored in the address table and an address requested by the second processor and output a comparison result; and
a stream controller configured to receive the comparison result from the address comparator and connect the second processor and the memory access switch according to the received comparison result.
14. The memory access device of claim 13 , wherein if the address requested by the second processor is included in the address table, the stream controller is configured to output data, corresponding to the address requested by the second processor, from the data buffer to the second processor.
15. The memory access device of claim 13 , wherein if the address requested by the second processor is not included in the address table, the stream controller is configured to output data, corresponding to the address requested by the second processor, from the memory device to the second processor.