IP Library Granted Patent US 8,244,993
Granted Patent B2
US 8,244,993 · App. 13/165,206 · Granted Aug 14, 2012

Memory chain

Assignee: Samsung Electronics Co., Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,244,993
App. No.
13/165,206
Granted
Aug 14, 2012
Kind
B2
Abstract

A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured to output a memory access command that is received by each of the memory devices in the chain and that selects a set of two or more of the memory devices to be accessed.

Claims (20)

1. A memory device having data inputs and data outputs configured to be coupled to memory devices in a chain, comprising:

a controller circuit configured to receive command packets including device selectors configured to identify selected ones of the memory devices in the chain to which data is transmitted from a memory controller, and configured to re-transmit data received from the memory controller to selected ones of the memory devices based on the device selectors.

2. A method of operating a memory system including a plurality of memory devices having respective data inputs coupled one to another in a chain, the method comprising:

transmitting a command packet from a memory controller to the plurality of memory devices, the command packet including device selectors configured to identify selected ones of the plurality of memory devices in the chain to which data is transmitted from the memory controller;

receiving the command packet at the ones of the plurality of memory devices to configure the selected ones of the plurality of memory devices for re-transmission of data received from the memory controller;

receiving the data transmitted from the memory controller at a first of the selected ones of the plurality of memory devices identified by the device selectors to provide received data; and

re-transmitting at least some of the received data to a next one of the selected ones of the plurality of memory devices identified by the device selectors.

3. The method according to claim 2 wherein re-transmitting at least some of the received data to a next one of the selected ones of the plurality of memory devices identified by the device selectors comprises re-transmitting all of the received data to the next one of the selected ones of the plurality of memory devices identified by the device selectors.

4. The method according to claim 3 wherein re-transmitting all of the received data further comprises:

asserting a valid out signal from the first of the selected ones of the plurality of memory devices to the next one of the selected ones of the plurality of memory devices identified by the device selectors during a time when the re-transmitting occurs.

5. The method according to claim 2 wherein re-transmitting at least some of the received data to a next one of the selected ones of the plurality of memory devices identified by the device selectors comprises re-transmitting to the next one only that data received by the first of the selected ones of the plurality of memory devices but not identified for storage therein by the device selectors.

6. The method according to claim 5 wherein re-transmitting all of the received data further comprises:

asserting a valid out signal from the first of the selected ones of the plurality of memory devices to the next one of the selected ones of the plurality of memory devices identified by the device selectors during a time when the re-transmitting occurs.

7. The method according to claim 6 wherein re-transmitting all of the received data further comprises:

asserting the valid out signal only during a time that data received by the first of the selected ones of the plurality of memory devices is re-transmitted.

8. A method of operating a memory system including a plurality of memory devices having respective data inputs coupled one to another in a chain, the method comprising:

transmitting a command packet from a memory controller to the plurality of memory devices, the command packet including device selectors configured to identify selected ones of the plurality of memory devices in the chain to which data is transmitted from the memory controller;

receiving the command packet at the ones of the plurality of memory devices to configure the selected ones of the plurality of memory devices for re-transmission of data received from the memory controller;

receiving the data transmitted from the memory controller at a first of the selected ones of the plurality of memory devices identified by the device selectors to provide received data; and

re-transmitting all of the received data from the first of the selected ones of the plurality of memory devices to a next one of the selected ones of the plurality of memory devices identified by the device selectors.

Continuity (2)
Continuation 11933445 · Nov 1, 2007
Related Publication 20110252164A1 · Oct 13, 2011