Multi-syndrome error correction circuit
In a particular embodiment, a forward error correction (FEC) decoder is disclosed that includes an input responsive to a communication channel to receive sampled bits from a continuous bit stream. The circuit device further includes a logic circuit to alternately provide sets of the received sampled bits from the continuous bit stream to one of a first syndrome generator and a second syndrome generator to correct errors in the sets of sampled bits to produce a decoded output related to the continuous bit stream.
1. A forward error correction (FEC) decoder comprising:
an input responsive to a communication channel to receive sampled bits from a continuous bit stream;
a logic circuit to alternately provide sets of the received sampled bits from the continuous bit stream to one of a first syndrome generator and a second syndrome generator to correct errors in the sets of sampled bits to produce a decoded output related to the continuous bit stream.
2. The FEC decoder of claim 1 , further comprising a data shifter circuit adapted to shift a number of bits corresponding to a particular forward error correction (FEC) code, wherein the data shifter circuit is responsive to the logic circuit to alternately shift the received number of bits to one of the first syndrome generator and the second syndrome generator.
3. The FEC decoder of claim 2 , wherein the FEC code comprises a (15, 10) Hamming code, and wherein the data shifter circuit is adapted to shift fifteen data bits.
4. The FEC decoder of claim 1 , wherein the continuous bit stream includes Bose-Chaudhuri-Hocquenghem (BCH) codes, and wherein the first and second syndrome generators are adapted to independently decode portions of the continuous bit stream using the BCH codes.
5. The FEC decoder of claim 1 , wherein the first syndrome generator and the second syndrome generator are adapted to correct a single bit error and double adjacent bit errors within each set of sampled bits.
6. The FEC decoder of claim 1 , further comprising selection logic adapted to alternately provide correction bits from one of the first syndrome generator or the second syndrome generator to correct data bits of the decoded output.
7. The FEC decoder of claim 6 , further comprising a stall circuit adapted to notify a host system when data at the output is valid.
8. A circuit device comprising:
a shifter circuit responsive to a communication channel to receive sampled bits related to a continuous bit stream and to shift the sampled bits serially with each clock cycle;
a first syndrome generator to correct at least one error within a first set of sampled bits to produce a first set of correction bits;
a second syndrome generator to correct at least one error within a second set of sampled bits to produce a second set of correction bits; and
a logic circuit adapted to control the shifter circuit to selectively shift the sampled bits to one of the first syndrome generator and the second syndrome generator to control the shifter circuit to produce to a corrected output related to the continuous bit stream.
9. The circuit device of claim 8 , wherein the logic circuit alternates between the first syndrome generator and the second syndrome generator periodically.
10. The circuit device of claim 9 , wherein the first syndrome generator is adapted to receive the first set of bits when the second syndrome generator is outputting the second set of correction bits to produce the corrected output.
11. The circuit device of claim 8 , further comprising:
a first multiplexing circuit responsive to the logic circuit to selectively provide the sampled bits to the first syndrome generator;
a second multiplexing circuit responsive to the logic circuit to selectively provide the sampled bits to the second syndrome generator; and
an output multiplexing circuit responsive to the logic circuit to selectively provide the first or the second set of corrected bits to an output.
12. The circuit device of claim 11 , wherein each of the first and second sets of sampled bits include a first number of data bits and a second number of error correcting bits.
13. The circuit device of claim 8 , wherein the logic circuit comprises:
a counter circuit to count a number of clock cycles; and
a toggle circuit coupled to the counter circuit and adapted to trigger a switch between the first and second syndrome generators when the number of clock cycles reaches a pre-determined number.
14. The circuit device of claim 8 , wherein the logic circuit further comprises a stall mechanism adapted to notify a host system when the corrected output is available at an output terminal.
15. The circuit device of claim 14 , where the stall mechanism comprises a register to indicate when corrected output includes valid data and to indicate when the data is corrupted.
16. A circuit device comprising:
a first syndrome to generate first correction bits;
a second syndrome to generate second correction bits;
an forward error correcting (FEC) shifter circuit responsive to a communication channel to receive sampled bits from a continuous bit stream, the continuous bit stream comprising forward error correction (FEC) data;
a counter circuit to count clock cycles and to reset after a pre-determined number of clock cycles; and
a logic circuit to control the FEC shifter circuit to shift the sampled bits serially with each clock cycle, the logic circuit to alternate shifting the sampled bits to one of the first syndrome generator and the second syndrome generator when the counter circuit resets;
wherein the first and second syndrome generators are adapted to use the FEC data to correct errors in the sampled bits and to generate, respectively, the first and second correction bits to produce a corrected output related to the continuous bit stream.
17. The circuit device of claim 16 , wherein the sampled data comprises a (15, 10) Hamming code including a data payload of fifteen bits with five error correction bits.
18. The circuit device of claim 17 , wherein the decoded output comprises ten error corrected bits for each data payload of fifteen bits.
19. The circuit device of claim 16 , further comprising:
a toggle circuit coupled to the counter circuit and adapted to produce a toggle output that changes each time the counter circuit is reset, the toggle output coupled to the FEC shifter circuit to control shifting of the sampled bits to one of the first syndrome generator or the second syndrome generator based on a value of the toggle output.
20. The circuit device of claim 19 , wherein the logic circuit further comprises an initial conditions module to configure initial conditions of the first and second syndrome generators and the toggle circuit.
21. The circuit device of claim 16 , wherein the logic circuit further comprises a stall circuit to notify a host system when the corrected output is available for sampling and to notify the host system when the corrected output is corrupt.