Symmetric STT-MRAM bit cell design

1. A symmetric Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell comprising:

a poly silicon layer;

a storage element; and

a bottom electrode (BE) plate,

wherein the storage element and bottom electrode (BE) plate are symmetric along a center line of the poly silicon layer.

2. The STT-MRAM bit cell of claim 1 , wherein the bottom electrode is a hexagonal bottom electrode.

3. The STT-MRAM bit cell of claim 1 , wherein the storage element is a magnetic tunnel junction (MTJ) storage element.

4. The STT-MRAM bit cell of claim 1 , further comprising:

a word line; and

a word line transistor coupled to the storage element.

5. The STT-MRAM bit cell of claim 4 , wherein the word line transistor is coupled in series with the storage element.

6. The STT-MRAM bit cell of claim 1 , further comprising:

a storage element seed;

a contact; and

a via interconnect,

wherein a center point of each of the storage element seed, the contact, and the via interconnect are matched.

7. A symmetric Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell array comprising:

a source line; and

a plurality of STT-MRAM bit cells arranged on a longitudinal axis that is perpendicular to a longitudinal axis of the source line and on opposite sides of the source line,

wherein the plurality of STT-MRAM bit cells are symmetrically arranged with respect to the source line, and wherein each of the STT-MRAM bit cells includes:

a poly silicon layer;

a magnetic tunnel junction (MTJ) storage element; and

a bottom electrode (BE) plate,

wherein the storage element and bottom electrode (BE) plate are symmetric along a center line of the poly silicon layer.

8. The STT-MRAM bit cell array of claim 7 , wherein the bottom electrode is a hexagonal bottom electrode.

9. The STT-MRAM bit cell array of claim 7 , wherein each of the STT-MRAM bit cells further comprises:

a word line; and

a word line transistor coupled to the storage element.

10. The STT-MRAM bit cell array of claim 9 , wherein the word line transistor is coupled in series with the storage element.

11. The STT-MRAM bit cell array of claim 7 , further comprising:

a storage element seed;

a contact; and

a via interconnect;

wherein a center point of each of the storage element seed, the contact, and the via interconnect are matched.

12. A method of forming a symmetric Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell array, the method comprising:

forming a plurality of STT-MRAM bit cells arranged on a longitudinal axis that is perpendicular to a longitudinal axis of a source line and on opposite sides of the source line such that the plurality of STT-MRAM bit cells are symmetrically arranged with respect to the source line, wherein each of the STT-MRAM bit cells includes:

a poly silicon layer;

a magnetic tunnel junction (MTJ) storage element; and

a bottom electrode (BE) plate,

wherein the storage element and bottom electrode (BE) plate are symmetric along a center line of the poly silicon layer.

13. The method of claim 12 , further comprising:

forming a storage element seed, a contact, and a via interconnect such that a center point of each of the storage element seed, the contact, and the via interconnect are matched.

14. The STT-MRAM bit cell of claim 1 , wherein the storage element and the bottom electrode (BE) plate are symmetric along a longitudinal axis extending perpendicular to the center line of the poly silicon layer.

15. The STT-MRAM bit cell of claim 6 , wherein the storage element and the bottom electrode (BE) plate are symmetric along a longitudinal axis extending perpendicular to the center line of the poly silicon layer.

16. The STT-MRAM bit cell of claim 15 , wherein the storage element seed, the contact, and the via interconnect are matched symmetrically with said longitudinal axis.

17. The STT-MRAM bit cell of claim 7 , wherein the center line of the poly silicon layer is perpendicular to the longitudinal axis of the plurality of STT-MRAM bit cells.

18. The STT-MRAM bit cell of claim 7 , wherein the center line of the poly silicon layer is perpendicular to the longitudinal axis of the plurality of STT-MRAM bit cells.

19. The STT-MRAM bit cell of claim 18 , wherein at least one of the plurality of STT-MRAM bit cells is arranged symmetric to the longitudinal axis of the plurality of STT-MRAM bit cells.

20. The STT-MRAM bit cell of claim 11 , wherein at least one of the plurality of STT-MRAM bit cells is arranged symmetric to the longitudinal axis of the plurality of STT-MRAM bit cells.

21. The STT-MRAM of claim 20 , wherein the storage element and the bottom electrode (BE) plate of the at least one of the plurality of STT-MRAM bit cells is symmetric along said longitudinal axis of the plurality of STT-MRAM bit cells.

22. The STT-MRAM of claim 21 , wherein the storage element seed, the contact, and the via interconnect are matched symmetrically with said longitudinal axis of the plurality of STT-MRAM bit cells.

23. The method of claim 12 , wherein forming at least one of the plurality of STT-MRAM bit cells includes forming the storage element and the bottom electrode (BE) plate of the at least one STT-MRAM bit cell symmetric along a longitudinal axis extending perpendicular to the center line of the poly silicon layer.

24. The method of claim 23 , wherein forming the at least one of the plurality of STT-MRAM cells further comprises: forming a storage element seed, a contact, and a via interconnect such that a center point of each of the storage element seed, the contact, and the via interconnect are matched.

25. The method of claim 24 , wherein forming the storage element seed, the contact, and the via interconnect forms the match symmetric with said longitudinal axis of the plurality of STT-MRAM bit cells.