Single input/output port radio frequency transceiver front end circuit
A front end circuit for coupling an antenna to a radio frequency (RF) transceiver for time domain duplex systems is disclosed. The front end circuit includes an antenna port, a power amplifier, a low noise amplifier, and a matching network. The output of the power amplifier and the input of the low noise amplifier are coupled to the matching network and connected in common to the antenna. The power amplifier and the low noise amplifier are activated and deactivated in sequence corresponding to the transmit and receive modes of the transceiver, and the matching network minimizes the effect that one has on the other at the designated operating frequency.
1. A radio frequency (RF) transceiver front end circuit with a predefined operating frequency for connecting a transceiver to an antenna, the front end circuit comprising:
an antenna port connectible to the antenna;
a common transmit and receive port;
a power amplifier including a first power amplifier transistor having a base, a collector, and an emitter;
a power amplifier input matching network coupling the common transmit and receive port to the power amplifier;
a low noise amplifier including a first low noise amplifier transistor having a base, a collector, and an emitter;
a low noise amplifier output matching network coupling the common transmit and receive port and the low noise amplifier; and
a matching circuit including a power amplifier output matching segment coupled to the collector of the first power amplifier transistor and the antenna port, and a low noise amplifier input matching segment coupled to the base of the first low noise amplifier transistor and the antenna port, the power amplifier matching segment having shared components with the low noise amplifier segment.
2. The front end circuit of claim 1 , wherein the low noise amplifier output matching network is chained with the power amplifier input matching network, an output impedance thereof being matched with the transceiver.
3. The front end circuit of claim 2 , wherein the low noise amplifier output matching network is coupled to the collector of the low noise amplifier and the base of the power amplifier transistor.
4. The front end circuit of claim 3 , further comprising:
a direct current bias switch coupled to the low noise amplifier.
5. The front end circuit of claim 2 , wherein:
the power amplifier input matching network defines a first network segment, a second network segment and a shared network segment, a junction between the first network segment and the second network segment defining a common point;
the low noise amplifier output matching network defines a third network segment and the shared network segment; and
the low noise amplifier output matching network is connected to the common point.
6. The front end circuit of claim 5 , further comprising:
a cascode transistor coupled to the low noise amplifier, the cascode transistor including a collector, a base, and an emitter;
wherein the low noise amplifier output matching network is coupled to the collector of the cascode transistor.
7. The front end circuit of claim 5 , wherein an impedance of the first network segment of the power amplifier input matching network is substantially equivalent to an impedance of the third network segment of the low noise amplifier output matching network.
8. The front end circuit of claim 5 , wherein the shared network segment further includes an electrostatic discharge inductor coupled to the common transmit and receive port and ground.
9. The front end circuit of claim 8 , wherein the third network segment of the low noise amplifier output matching network includes a matching capacitor.
10. The front end circuit of claim 1 , wherein the power amplifier has a plurality of amplification stages including a plurality of interconnected power amplifier transistors.
11. The front end circuit of claim 1 , wherein the low noise amplifier has a plurality of amplification stages including a plurality of interconnected low noise amplifier transistors.