IP Library Granted Patent US 8,266,238
Granted Patent B2
US 8,266,238 · App. 11/646,083 · Granted Sep 11, 2012

Memory mapped network access

Assignee: Intel Corporation
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Quick Facts
Patent No.
US 8,266,238
App. No.
11/646,083
Granted
Sep 11, 2012
Kind
B2
Abstract

The present disclosure relates to memory access, and specifically to memory access utilizing internet protocol (IP) addressing semantics. Various embodiments, methods, apparatus and systems are provided that allow a system to detect that a memory access has been attempted involving a region of memory that is mapped to a network device; and to perform the memory access utilizing, at least in part, the networked device and a network interface. Other embodiments may be described and claimed.

Claims (39)

1. A method comprising:

mapping, by a virtual machine monitor of a system, a plurality of virtual memory addresses within a region of a virtual memory address space of a virtual machine to a plurality of internet protocol (IP) addresses, wherein the plurality of virtual memory addresses being mapped correspond to physical memory locations beyond a range of physical memory addresses available on the system, and wherein the virtual machine is disposed on the system;

trapping, by the virtual machine monitor, a memory read or write access made by a guest operating system;

determining, by the virtual machine monitor, that the memory read or write access occurs for a memory address that is greater than the range of physical memory addresses available on the system, wherein the memory read or write access involves one of the plurality of virtual memory addresses within said region of the virtual memory address space that is mapped to one of the plurality of IP addresses; and

transmitting, by the virtual machine monitor, a data read or write request corresponding to the memory read or write access to a network device associated with the one of the plurality of IP addresses corresponding to the one of the plurality of the virtual memory addresses.

2. The method of claim 1 , wherein the memory access facilitates inter-process communication.

3. The method of claim 1 , wherein the range of physical memory addresses available on the system includes 2 44 addresses, and the range of virtual memory addresses provided to the guest operating system includes 2 64 addresses.

4. The method of claim 1 , wherein the IP addresses are Ipv6 addresses.

5. The method of claim 1 , wherein mapping comprises mapping, by the virtual machine monitor, each of the plurality of virtual memory addresses within the region of the virtual memory address space of the virtual machine to a corresponding IP address of the plurality of internet protocol (IP) addresses on the one-to-one basis.

6. The method of claim 1 , wherein mapping comprises mapping by the virtual machine monitor, multiple ones of the plurality of virtual memory addresses within the region of the virtual memory address space of the virtual machine to one of the plurality of internet protocol (IP) addresses, and wherein mapping further comprises associating multiple offsets to the mapped IP address for the multiple ones of the plurality of virtual memory addresses.

7. A method comprising:

mapping, by a hypervisor of a computing device, a plurality of virtual memory addresses within a region of a virtual memory address space of a virtual machine to a plurality of internet protocol (IP) addresses, wherein the virtual memory addresses being mapped correspond to physical memory locations beyond a range of physical memory addresses available on the computing device, and wherein the virtual machine is disposed on the computing device;

trapping, by the hypervisor, a memory read or write access by a guest operating system;

determining, by the hypervisor, whether the memory read or write access occurs for a memory address that is greater than the range of physical memory addresses available on the computing device, wherein the memory read or write access involves one of the plurality of virtual memory addresses mapped to one of the plurality of IP addresses;

upon determining that the memory read or write access occurs for the memory address that is greater that the range of physical memory addresses available on the computing device, forwarding, by the hypervisor, a data read or write request corresponding to the memory read or write access to a network device associated with the one of the plurality of IP addresses corresponding to the one of the plurality of virtual memory addresses; and

upon determining that the memory read or write access occurs for the memory address that is within the range of physical memory addresses available on the computing device, allowing the memory read or write access to proceed without said forwarding.

8. The method of claim 7 , wherein the memory read or write access facilitates communication between the virtual machine and another virtual machine disposed on the computing device or another computing device.

9. The method of claim 8 , wherein trapping the memory read or write access includes utilizing a hardware feature of the computing device running the hypervisor.

10. The method of claim 9 , wherein the hardware feature of the computing device is a portion of Intel Virtualization Technology.

11. The method of claim 7 , wherein the hypervisor keeps the guest operating system unaware of whether the memory read or write access is facilitated by the forwarding of the corresponding data read or write request.

12. An apparatus comprising:

a physical memory configured to store data;

a chipset configured to support a virtual machine monitor that is configured to:

map a plurality of virtual memory addresses within a region of a virtual memory address space of a virtual machine to a plurality of network addresses, wherein the plurality of virtual memory addresses being mapped correspond to physical memory locations beyond a range of physical memory addresses available on the physical memory of the apparatus, and wherein the virtual machine is disposed on the apparatus;

trap a memory read or write access made by a guest operating system;

determine that the memory read or write access occurs for a memory address that is greater than the range of physical memory addresses available on the physical memory of the apparatus, wherein the memory read or write access involves one of the plurality of virtual memory addresses within said region of the virtual memory address space that is mapped to one of the plurality of network addresses; and

forward a data read or write request corresponding to the memory read or write access to a network device associated with the one of the plurality of network addresses corresponding to the one of the plurality of the virtual memory addresses; and

a network interface coupled with the chipset and configured to enable the virtual machine monitor to forward the memory read or write request by transmitting the memory read or write request to the network device associated with the one of the plurality of network addresses, wherein the network device comprises a network memory configured to store data.

13. The apparatus of claim 12 , wherein the virtual machine monitor is further configured to divide the virtual memory address space between the physical memory of the apparatus and the network memory of the network device.

14. The apparatus of claim 13 , wherein the virtual machine monitor is further configured to allow a memory read or write access for a memory address that is within the range of physical memory addresses available on the physical memory of the apparatus to proceed without said transmitting the corresponding data read or write request to the network device.

15. The apparatus of claim 12 , wherein the virtual machine monitor is a hypervisor.

16. The apparatus of claim 12 , wherein the chipset is further configured to map each of the plurality of virtual memory addresses within the region of the virtual memory address space of the virtual machine to a corresponding network address of the plurality of network addresses on the one-to-one basis.

17. The apparatus of claim 12 , wherein the chipset is further configured to map multiple ones of the plurality of virtual memory addresses within the region of the virtual memory address space of the virtual machine to one of the plurality of network addresses, and associate multiple offsets to the mapped network address for the multiple ones of the plurality of virtual memory addresses.

18. An article comprising:

a tangible non-transitory computer-readable storage medium having a plurality of machine accessible instructions, wherein the instructions, in response to execution of the instructions by a computing device, cause a virtual machine monitor of the computing device to:

map a plurality of virtual memory addresses within a region of a virtual memory address space of a virtual machine to a plurality of internet protocol (IP) addresses, wherein the virtual memory addresses being mapped correspond to physical memory locations beyond a range of physical memory addresses available on the computing device, and wherein the virtual machine is disposed on the computing device;

trap a memory read or write access made by a guest operating system;

determine that the memory read or write access occurs for a memory address that is greater than the range of physical memory addresses available on the computing device, wherein the memory read or write access involves one of the plurality of virtual memory addresses within the region of the virtual memory address space that is mapped to one of the plurality of IP addresses; and

transmit a data read or write request corresponding to the memory read or write access to a network device associated with the one of the plurality of IP addresses corresponding to the one of the plurality of virtual memory addresses.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 1, 2007
From: ZIMMER, VINCENT J.; ROTHMAN, MICHAEL A.
To: INTEL CORPORATION
Reel/Frame 019231/0731 →
Continuity (1)
Related Publication 20080162680A1 · Jul 3, 2008