IP Library Granted Patent US 8,269,469
Granted Patent B2
US 8,269,469 · App. 12/540,281 · Granted Sep 18, 2012

Equalizing method and circuit for ultracapacitors

Assignee: Ivus Industries, LLC
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Quick Facts
Patent No.
US 8,269,469
App. No.
12/540,281
Granted
Sep 18, 2012
Kind
B2
Abstract

An equalizing method for ultracapacitor cell packs and/or series connected ultracapacitors.

Claims (44)

1. An ultracapacitor charging method for charging a series connected string of ultracapacitor cells having a plurality of balancing circuits, said method comprising the steps of:

a. specifying a voltage balance hysteresis as variable V_BAL_HYST;

b. charging said string of ultracapacitor cells;

c. turning all balancing circuits off;

d. measuring the voltage of each ultracapacitor cell to determine the smallest measured cell voltage;

e. storing said smallest measured cell voltage as variable V min in a digital controller; and

f. for each ultracapacitor cell in the series connected string iteratively performing the following steps by said digital controller:

i) measuring the voltage of the ultracapacitor cell to set Vcell;

ii) computing the difference of Vcell and V min ;

iii) comparing difference of Vcell and V min to V_BAL_HYST, wherein if the difference of Vcell and V min >V_BAL_HYST, then turning on the balancing circuit for the cell, draining current from the cell.

2. The ultracapacitor charging method of claim 1 , wherein the step of measuring the voltage of each ultracapacitor cell to determine the smallest measured cell voltage is performed via an analog measurement circuit.

3. The ultracapacitor charging method of claim 1 , wherein the step of charging said string of ultracapacitor cells is performed by a charger.

4. The ultracapacitor charging method of claim 1 , wherein the step of specifying a voltage balance hysteresis as variable V_BAL_HYST is performed by said digital controller.

5. The ultracapacitor charging method of claim 1 , wherein after a predetermined period of time has passed, steps c, d, e and f are repeated.

6. An ultracapacitor charging method for charging a series connected string of ultracapacitor cells having a plurality of balancing circuits, said method comprising the steps of:

a. specifying a voltage balance hysteresis as variable V_BAL_HYST;

b. charging said string of ultracapacitor cells;

c. establishing a predetermined time interval; and

d. performing the following steps for a period of time equal to said time interval:

turning all balancing circuits off;

ii. measuring the voltage of each ultracapacitor cell to determine the smallest measured cell voltage;

iii. storing said smallest measured cell voltage as variable V min in a digital controller;

iv. for each ultracapacitor cell in the series connected string iteratively performing the following steps by said digital controller:

a) measuring the voltage of the ultracapacitor cell to set Vcell;

b) computing the difference of Vcell and V min ;

c) comparing difference of Vcell and V min to V_BAL_HYST, wherein if the difference of Vcell and V min >V_BAL_HYST, then turning on the balancing circuit for the cell, draining current from the cell; and

e. repeating step d after said period of time has passed.

7. The ultracapacitor charging method of claim 6 , wherein the step of measuring the voltage of each ultracapacitor cell to determine the smallest measured cell voltage is performed via an analog measurement circuit.

8. The ultracapacitor charging method of claim 6 , wherein the step of charging said string of ultracapacitor cells is performed by a charger.

9. The ultracapacitor charging method of claim 6 , wherein the step of specifying a voltage balance hysteresis as variable V_BAL_HYST is performed by said digital controller.

10. An apparatus for charging a series connected string of ultracapacitor cells, said apparatus comprising:

a charger for charging said string of ultracapacitor cells;

a plurality of balancing circuits for draining current from the cell; and

a digital controller, said digital controller specifying a voltage balance hysteresis as variable V_BAL_HYST, said digital controller turning all balancing circuits off, determining which cell has the smallest cell voltage (V min ), wherein as the ultracapacitor cells charge said digital controller monitors the voltage of each of the ultracapacitor cells, turning the corresponding balancing circuit on for any ultracapacitor cells where the difference between the voltage of the ultracapacitor cell and V min >V_BAL_HYST.

11. The apparatus of claim 10 , wherein an analog measurement circuit is utilized to measure the voltage of each ultracapacitor cell so that said digital controller can determine the smallest measured cell voltage.

12. The apparatus of claim 10 , further comprising an artificial time delay for providing said ultracapacitor cells with an adequate time to balance, wherein after said time delay said digital controller turning all balancing circuits off, determining which cell has the smallest cell voltage (V min ), wherein as the ultracapacitor cells charge said digital controller monitors the voltage of each of the ultracapacitor cells, turning the corresponding balancing circuit on for any ultracapacitor cells where the difference between the voltage of the ultracapacitor cell and V min >V_BAL_HYST.

13. The apparatus of claim 10 , wherein said plurality of balancing circuits comprises at least one first balancing circuit which allows current to be drained from each ultracapacitor cell in said string.

14. The apparatus of claim 11 , wherein said at least one first balancing circuit comprises a plurality of resistors, at least one MOSFET, and at least one zener diode.

15. The apparatus of claim 11 , wherein said at least one first balancing circuit comprises a plurality of resistors and at least one transistor.

16. The apparatus of claim 15 , wherein said at least one transistor is at least one bi-polar junction transistor.

17. The apparatus of claim 15 , wherein said at least one transistor is at least one phototransistor.

18. The apparatus of claim 15 , wherein said at least one transistor is at least one insulated gate bipolar transistor.

19. The ultracapacitor charging method of claim 1 , further comprising the step of establishing a predetermined time interval.

20. The ultracapacitor charging method of claim 19 , wherein said steps c, d, e and f are performed for a period of time equal to said time interval, and wherein step d is repeated after said period of time has passed.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 6, 2017
From: IVUS INDUSTRIES, LLC
To: DAN J. AND DENISE L. COSTA 1997 FAMILY TRUST
Reel/Frame 041889/0378 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME (LLC INSTEAD OF INC) PREVIOUSLY RECORDED ON REEL 023343 FRAME 0430. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT OF RIGHTS, TITLE AND INTEREST IN INVENTION. Recorded Oct 27, 2010
From: CEGNAR, ERIK; JESSUP, FRED; MAUGHAN, MICHAEL; ALEXANDER, DAVID
To: IVUS INDUSTRIES, LLC
Reel/Frame 025205/0805 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2009
From: CEGNAR, ERIK; JESSUP, FRED; MAUGHAN, MICHAEL; ALEXANDER, DAVID
To: IVUS INDUSTRIES, INC.
Reel/Frame 023343/0430 →
Continuity (2)
Provisional Application 61088213 · Aug 12, 2008
Related Publication 20100039072A1 · Feb 18, 2010