Bootstrap circuit

1. A bootstrap circuit comprising:

a first transistor connecting a first power supply with an output terminal; and

a second transistor applying a first input signal to a gate node of the first transistor and having a conductivity type identical to that of the first transistor,

wherein a second input signal obtained by inverting a level of the first input signal, delaying the inverted signal, and adding a direct current bias to the delayed signal is inputted to a gate node of the second transistor.

2. The bootstrap circuit according to claim 1 , further comprising:

a signal delay circuit; and

a direct current bias circuit,

wherein the signal delay circuit and the direct current bias circuit are connected in series to the gate node of the second transistor and arranged for a level-inverted signal of the first input signal.

3. The bootstrap circuit according to claim 1 , wherein, the signal delay circuit is connected to the gate node of the second transistor, and the direct current bias circuit is connected to a source or drain node of the second transistor.

4. The bootstrap circuit according to claim 1 , further comprising a third transistor connecting a second power supply with the output terminal and having a conductivity type identical to that of the first transistor, wherein a level-inverted signal of the first input signal is applied to a gate node of the third transistor.

5. The bootstrap circuit according to claim 2 , further comprising a fourth transistor connecting the second power supply with an output node of the signal delay circuit and having a conductivity type identical to that of the first transistor, wherein a gate node of the fourth transistor is connected to the gate node of the first transistor.

6. The bootstrap circuit according to claim 2 , wherein the direct current bias circuit adds a direct current bias voltage that is at least equal to or more than a threshold voltage of the second transistor.

7. The bootstrap circuit according to claim 2 , wherein the direct current bias circuit comprises a capacitive element connecting input and output nodes of the direct current bias circuit and a switch element connecting the output node thereof and a bias voltage supply.

8. The bootstrap circuit according to claim 2 ,

wherein the direct current bias circuit comprises:

a first capacitive element connecting input and output nodes of the direct current bias circuit;

a second capacitive element having one end thereof supplied with an inverted signal of a signal inputted to the input node;

a first switch element connecting the output node with a bias voltage supply; and

a second switch element connecting the other end of the second capacitive element with the bias voltage supply, and

wherein a gate node of the first switch element and the other end of the second capacitive element are connected to each other, and a gate node of the second switch element and the output node are connected to each other.

9. The bootstrap circuit according to claim 2 , wherein the signal delay circuit comprises a plurality of inverting circuits connected in series.

10. The bootstrap circuit according to claim 2 , wherein the signal delay circuit comprises: a series resistor connecting input and output nodes of the signal delay circuit; and a capacitive element having one end connected to the output node thereof and the other end supplied with a fixed potential.

11. The bootstrap circuit according to claim 10 , wherein the series resistor comprises a transistor having one end as a source node and the other end as a drain node.

12. The bootstrap circuit according to claim 10 , the capacitive element comprises a transistor having one end as source and drain nodes and the other end as a gate node.

13. A level shift circuit comprising the bootstrap circuit according to claim 1 as an output circuit.

14. A word line driving circuit comprising the bootstrap circuit according to claim 1 as an output circuit.