IP Library Granted Patent US 8,276,025
Granted Patent B2
US 8,276,025 · App. 12/478,679 · Granted Sep 25, 2012

Block interleaving scheme with configurable size to achieve time and frequency diversity

Assignee: Maxim Integrated Products, Inc.
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Quick Facts
Patent No.
US 8,276,025
App. No.
12/478,679
Granted
Sep 25, 2012
Kind
B2
Abstract

An embodiment is a method and apparatus to interleave data. A demultiplexer demultiplexes an input packet having N bits into L sub-packets on L branches. M flipping blocks flip M of the L sub-packets. M is smaller than L. L sub-interleavers interleave the (L-M) sub-packets and the M flipped sub-packets. A concatenator concatenates the interleaved sub-packets to form an output packet.

Claims (35)

1. An apparatus comprising:

a demultiplexer to demultiplex an input packet having N bits into L sub-packets on L branches;

M flipping blocks coupled to the demultiplexer to flip M of the L sub-packets, M being smaller than L;

L sub-interleaves coupled to the demultiplexer and the M flipping blocks to interleave the (L-M) sub-packets and the M flipped sub-packets; and

a concatenate coupled to the L sub-interleaves to concatenate the interleaved sub-packets to form an output packet; wherein L and M are integers greater than or equal to one.

2. The apparatus of claim 1 wherein the demultiplexer operates in a normal mode and a robust mode.

3. The apparatus of claim 2 wherein in the normal mode the input packet is switched at a rate of every L bits for each of the L branches.

4. The apparatus of claim 2 wherein in the robust mode the input packet is repeated L times.

5. The apparatus of claim 4 wherein in K of the L branches the input packet is read from bit N 0 of the N bits in a wrap-around manner.

6. The apparatus of claim 1 wherein each of the M flipping blocks reverses a bit order of one of the L sub-packets from end to beginning.

7. The apparatus of claim 1 wherein each of the L sub-interleavers writes the sub-packet row-by-row in a matrix having R rows and C columns and reads the sub-packet from the matrix in a helical scan manner.

8. The apparatus of claim 7 wherein C is equal to a product of number of symbols and number of carriers divided by a constant.

9. The apparatus of claim 8 wherein R is equal to 10 and the constant is equal to 40.

10. The apparatus of claim 1 wherein the concatenator concatenates the L sub-packets on a sub-packet basis.

11. A method comprising: demultiplexing an input packet having N bits into L sub-packets on L branches; flipping M of the L sub-packets, M being smaller than L; interleaving the (L-M) sub-packets and the M flipped sub-packets; and concatenating the interleaved sub-packets to form an output packet; wherein L and M are integers greater than or equal to one.

12. The method of claim 11 wherein demultiplexing comprises operating in a normal mode and a robust mode.

13. The method of claim 12 wherein in the normal mode the input packet is switched at a rate of every L bits for each of the L branches.

14. The method of claim 12 wherein in the robust mode the input packet is repeated L times.

15. The method of claim 14 wherein in K of the L branches the input packet is read from bit N 0 of the N bits in a wrap-around manner.

16. The method of claim 11 wherein flipping comprises reversing a bit order of one of the L sub-packets from end to beginning.

17. The method of claim 11 wherein interleaving comprises:

writing the sub-packet row-by-row in a matrix having R rows and C columns; and

reading the sub-packet from the matrix in a helical scan manner.

18. The method of claim 17 wherein C is equal to a product of number of symbols and number of carriers divided by a constant.

19. The method of claim 18 wherein R is equal to 10 and the constant is equal to 40.

20. The method of claim 11 wherein concatenating comprises concatenating the L sub-packets on a sub-packet basis.

21. A system comprising:

a forward error correction (FEC) encoder to encode an input data stream, the FEC encoder comprising an interleaver to interleave an input packet from the input data stream, the interleaver comprising:

a demultiplexer to demultiplex the input packet having N bits into L sub-packets on L branches;

M flipping blocks coupled to the demultiplexer to flip M of the L sub-packets, M being smaller than L;

L sub-interleaves coupled to the demultiplexer and the M flipping blocks to interleave the (L-M) sub-packets and the M flipped sub-packets; and

a concatenate coupled to the L sub-interleaves to concatenate the interleaved sub-packets to form an output packet;

a modulator coupled to the FEC encoder to modulate the output packet; and

a power spectral density (PSD) shaping module coupled to the modulator to spectrally shape the modulated output packet; wherein L and M are integers greater than or equal to one.

22. The system of claim 21 wherein the modulator is an orthogonal frequency division multiplexing (OFDM) modulator.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2011
From: RAZAZIAN, KAVEH; KAMALIZAD, AMIR HOSEIN; UMARI, MAHER
To: MAXIM INTEGRATED PRODUCTS, INC.
Reel/Frame 025767/0681 →
Continuity (2)
Provisional Application 61059707 · Jun 6, 2008
Related Publication 20090307541A1 · Dec 10, 2009