IP Library › Granted Patent US 8,286,108

Granted Patent B2

US 8,286,108 · App. 12/651,418 · Granted Oct 9, 2012

System and method for synthesis reuse

Assignee: Cadence Design Systems, Inc.

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Quick Facts

Patent No.: US 8,286,108
App. No.: 12/651,418
Granted: Oct 9, 2012
Kind: B2

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Abstract

A method of synthesis of multiple implementations of a design is provided comprising: translating a model of the design to a first output model compliant with first constraints; and translating the model of the design to a second output model compliant with second constraints.

Claims (86)

1. A method of synthesis of multiple implementations of an integrated circuit design, comprising:

providing a model of the design comprising an algorithm implemented by the design;

using a computer system to perform steps of:

providing a first constraint file including at least one first constraint upon implementation of the model;

inputting the model of the design and the first constraint file to a synthesis tool;

receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint;

providing a second constraint file including at least one second constraint upon implementation of the model;

inputting the model of the design and the second constraint file to the synthesis tool;

receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one second constraint;

changing the model of the design to produce a changed model of the design;

inputting the changed model of the design and the first constraint file to the synthesis tool; and

receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint.

2. The method of claim 1 , wherein the first constraint file including at least one first constraint is directed to higher speed operation of the integrated circuit than is the second constraint file including at least one second constraint.

3. The method of claim 1 , wherein the first constraint file including at least one first constraint is directed to lower power operation of the integrated circuit than is the second constraint file including at least one second constraint.

4. The method claim 1 , wherein the first constraint file including at least one first constraint is directed to higher fidelity performance of the integrated circuit than is the second constraint file including at least one second constraint.

5. A method of synthesis of multiple implications of an integrated circuit design, comprising:

providing a model of the design comprising an algorithm implemented by the design;

using a computer system to perform steps of:

providing a first constraint file including at least one first constraint upon implementation of the model;

inputting the model of the design and the first constraint file to a synthesis tool;

receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint;

providing a second constraint file including at least one second constraint upon implementation of the model;

inputting the model of the design and the second constraint file to the synthesis tool;

receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one second constraint;

changing the model of the design to produce a changed model of the design;

inputting the changed model of the design and the constraint files to the synthesis tool; and

receiving as output from the synthesis tool an output model of the design for implementing the design to meet both the constraint files.

6. The method of claim 5 , wherein the first constraint file including at least one first constraint is directed to higher speed operation of the integrated circuit than is the second constraint file including at least one second constraint.

7. The method of claim 5 , wherein the first constraint file including at least one first constraint is directed to tower power operation of the integrated circuit than is the second constraint file including at least one second constraint.

8. The method claim 5 , wherein the first constraint file including at least one first constraint is directed to higher fidelity performance of the integrated circuit than is the second constraint file including at least one second constraint.

9. A computer system, comprising: a CPU; a storage; and a bus coupling the CPU to the storage; wherein the storage stores a code for execution by the CPU, the code performing a method of synthesis of multiple implementations of an integrated circuit design comprising:

receiving a model of the design comprising an algorithm implemented by the design;

receiving a first constraint file including at least one first constraint upon implementation of the model;

inputting the model of the design and the first constraint file to a synthesis tool;

receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint;

receiving a second constraint file including at least one second constraint upon. implementation of the model;

inputting the model of the design and the second constraint file to the synthesis tool;

receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one second constraint;

changing the model of the design to produce a changed model of the design;

inputting the changed model of the design and the first constraint file to the synthesis tool; and

receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint.

10. The system of claim 9 , wherein the first constraint file including at least one first constraint is directed to higher speed operation of the integrated circuit than is the second constraint file including at least one second constraint.

11. The system of claim 9 , wherein the first constraint file including at least one first constraint is directed to lower power operation of the integrated circuit than is the second constraint file including at least one second constraint.

12. The system of claim 9 , wherein the first constraint file including at least one first constraint is directed to higher fidelity performance of the integrated circuit than is the second constraint file including at least one second constraint.

13. A computer system, comprising: a CPU; a storage; and a bus coupling the CPU to the storage; wherein the storage stores a code for execution by the CPU, the code performing a method of synthesis of multiple implementations of an integrated circuit design comprising:

receiving a model of the design comprising an algorithm implemented by the design;

receiving a first constraint file including at least one first constraint upon implementation of the model;

inputting the model of the design and the first constraint file to a synthesis tool;

receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint;

receiving a second constraint file including at least one second constraint upon implementation of the model;

inputting the model of the design and the second constraint file to the synthesis tool;

receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one second constraint;

changing the model of the design to produce a changed model of the design;

inputting the changed model of the design and the constraint files to the synthesis tool; and

receiving as output from the synthesis tool an output model of the design for implementing the design to meet both the constraint files.

14. The system of claim 13 , wherein the first constraint file including at least one first constraint is directed to higher speed operation of the integrated circuit than is the second constraint file including at least one second constraint.

15. The system of claim 13 , wherein the first constraint file including at least one first constraint is directed to tower power operation of the integrated circuit than is the second constraint file including at least one second constraint.

16. The system of claim 13 , wherein the first constraint file including at least one first constraint is directed to higher fidelity performance of the integrated circuit than is the second constraint file including at least one second constraint.

17. A computer readable storage device storing code for performing a method of synthesis of multiple implementations of an integrated circuit design, wherein the method comprises:

receiving a model of the design comprising an algorithm implemented by the design;

receiving a first constraint file including at least one first constraint upon implementation of the model;

inputting the model of the design and the first constraint file to a synthesis tool;

receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint;

receiving a second constraint file including at least one second constraint upon implementation of the model;

inputting the model of the design and the second constraint file to the synthesis tool;

receiving as output the synthesis tool an output model of the design for implementing the design to meet the at least one second constraint;

changing the model of the design to produce a changed model of the design;

inputting the changed model of the design and the first constraint to the synthesis tool; and

receiving as output from the synthesis tool an output model of the design for implementing the design to meet the at least one first constraint.

18. The computer readable storage device of claim 17 , wherein the first constraint file including at least one first constraint is directed to higher speed operation of the integrated circuit than is the second constraint file including at least one second constraint.

19. The computer readable storage device of claim 17 , wherein the first constraint file including at least one first constraint is directed to lower power operation of the integrated circuit than is the second constraint file including at least one second constraint.

20. The computer readable storage device of claim 17 , wherein the first constraint file including at least one first constraint is directed to higher fidelity performance of the integrated circuit than is the second constraint file including at least one second constraint.

21. A computer readable storage device storing code for performing a method of synthesis of multiple implementations of an integrated circuit design, wherein the method comprises: