IP Library Granted Patent US 8,296,608
Granted Patent B2
US 8,296,608 · App. 12/748,807 · Granted Oct 23, 2012

Memory device

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,296,608
App. No.
12/748,807
Granted
Oct 23, 2012
Kind
B2
Abstract

A first module calculates a failure occurrence risk index of each data storage area address. A second module calculates a power saving index of each data storage area address. A third module calculates an access speed index per unit data volume necessary to access each data storage area address. A fourth module generates a distribution table that represents the failure occurrence risk index, the power saving index, and the access speed index for each candidate address, with respect to data to be distributed. A fifth module selects a candidate address in the distribution table such that the power saving index and the access speed index meet restricting conditions and the failure occurrence risk index is minimized, and distributes the data to the candidate address.

Claims (12)

1. A memory device comprising:

a first module configured to calculate a failure occurrence risk index of each data storage area address;

a second module configured to calculate a power saving index of each data storage area address;

a third module configured to calculate an access speed index per unit data volume necessary to access each data storage area address;

a fourth module configured to generate a distribution table that represents the failure occurrence risk index, the power saving index, and the access speed index for each candidate address, with respect to data to be distributed; and

a fifth module configured to select a candidate address in the distribution table such that the power saving index and the access speed index meet restricting conditions and the failure occurrence risk index is minimized, and distribute the data to the candidate address, wherein the failure occurrence risk index is calculated by using:

a table representing a failure occurrence probability of a failure portion address;

a first model that associates the failure occurrence probability of each data storage area address with the failure portion address; and

a second model that associates a degree of influence on a user with the failure occurrence probability of each data storage area address.

2. The device according to claim 1 , further comprising a sixth module configured to monitor, by symptom detection of health monitoring, a failure occurrence condition including one of a failure sector generation log and a canary device abnormality sensing log, and update the table representing the failure occurrence probability of the failure portion address in accordance with the failure occurrence condition.

3. The device according to claim 1 , wherein the data storage area is divided into a plurality of areas, power supply to each of the plurality of areas being individually controllable, and

the device further comprises a seventh module which calculates, as the power saving index, power consumption necessary to move or copy a data aggregate to be moved or copied, in accordance with a volume of the data aggregate and a way the data storage area is divided.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2010
From: HIROHATA, KENJI; YONEZAWA, MINORU; MORITA, CHIE; NISHIKAWA, TAKEICHIRO; NAKATSUGAWA, MINORU; MUKAI, MINORU
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 024325/0694 →
Priority Claims (1)
JP 2009-083345 · Mar 30, 2009 · national
Continuity (1)
Related Publication 20100251039A1 · Sep 30, 2010