Sense amplifier and semiconductor apparatus including the same
A sense amplifier is configured to transfer data on a first data I/O line to a second data I/O line or to transfer data on the second data I/O line to the first data I/O line. The first data I/O line is substantially continuously coupled to the second data I/O line during an active operation.
1. A sense amplifier configured to transfer data on first data I/O lines to second data I/O lines or to transfer data on the second data I/O lines to the first data I/O lines, wherein the first data I/O line is coupled to the second data I/O line continuously during an active operation.
2. The sense amplifier of claim 1 , wherein the sense amplifier is configured to couple the first and second data I/O lines in response to an I/O switch signal enabled to select the second data I/O line.
3. The sense amplifier of claim 2 , wherein the I/O switch signal is generated from an active signal or a row selection signal.
4. A sense amplifier comprising:
a data line connecting unit configured to couple first data I/O lines to second data I/O lines in response to an I/O switch signal; and
a hybrid data transfer unit configured to amplify the first data I/O line in response to a sense amplifier enable signal.
5. The sense amplifier of claim 4 , wherein the I/O switch signal is generated from an active signal or a row selection signal.
6. The sense amplifier of claim 4 , wherein the sense amplifier enable signal is generated from a read or write command.
7. The sense amplifier of claim 6 , wherein the sense amplifier enable signal is generated from a column decoder block.
8. The sense amplifier of claim 4 , wherein the hybrid data transfer unit is configured to differentially amplify data on the first data I/O lines to transfer the data to the second data I/O lines or differentially amplify the first data I/O lines based on data transferred from the second data I/O lines, when the sense amplifier enable signal is enabled.
9. A semiconductor apparatus comprising:
a sense amplifier configured to transfer data between first and second data I/O lines in response to an I/O switch signal and a driving sense amplifier enable signal; and
a precharge unit configured to precharge the first data I/O lines in response to a driving precharge signal,
wherein the driving sense amplifier enable signal and the driving precharge signal are generated by one or more elements in a circuit area between a plurality of memory blocks.
10. The semiconductor apparatus of claim 9 , wherein the sense amplifier is configured to couple first and second data I/O lines to each other in response to the I/O switch signal and to differentially amplify the first data I/O lines in response to the driving sense amplifier enable signal.
11. The semiconductor apparatus of claim 9 , wherein the I/O switch signal is generated from an active signal or a row selection signal.
12. The semiconductor apparatus of claim 9 , wherein the semiconductor apparatus further includes a driver block located in the circuit area between the memory blocks to receive a sense amplifier enable signal, a precharge signal, and the I/O switch signal to generate the driving sense amplifier enable signal and the driving precharge signal.
13. The semiconductor apparatus of claim 12 , wherein the sense amplifier enable signal is generated from a read or write command.
14. The semiconductor apparatus of claim 12 , wherein the sense amplifier enable signal and the precharge signal are generated from a column decoder block.
15. The semiconductor apparatus of claim 9 , wherein the precharge unit is configured to precharge the first data I/O lines with a core voltage in response to the driving precharge signal.
16. A semiconductor apparatus comprising:
first and second memory blocks to which a plurality of bit lines are assigned;
a bit line sense amplifier configured to amplify the plurality of bit lines;
first data I/O lines configured to be coupled to the plurality of bit lines;
a sense amplifier configured to transfer data between the first data I/O lines and a second data I/O lines and to maintain an electrical connection of the first data I/O lines and the second data I/O lines substantially during an active operation; and
a precharge unit configured to precharge the first data I/O line,
wherein a sense amplifier enable signal to control the sense amplifier and a precharge signal to control the precharge unit are generated in a column decoder block.
17. The semiconductor apparatus of claim 16 , wherein the semiconductor apparatus further includes a driver block configured to receive the sense amplifier enable signal, the precharge signal, and an I/O switch signal to generate a driving sense amplifier enable signal and a driving precharge signal.
18. The semiconductor apparatus of claim 17 , wherein the driver block is located in a circuit area between the first and second memory blocks.
19. The semiconductor apparatus of claim 17 , wherein the sense amplifier is configured to couple the first and second data I/O lines to each other in response to the I/O switch signal and to differentially amplify the first data I/O line in response to the driving sense amplifier enable signal.
20. The semiconductor apparatus of claim 17 , wherein the I/O switch signal is generated from an active signal or a row selection signal.
21. The semiconductor apparatus of claim 16 , wherein the precharge unit is configured to precharge the first data I/O lines with a core voltage.
22. A semiconductor apparatus comprising:
a sense amplifier configured to transfer data between first data I/O lines and second data I/O lines; and
a precharge unit configured to precharge the first data I/O lines and the second data I/O lines,
wherein an electrical connection between the first data I/O lines and the second data I/O lines is maintained during an active operation.
23. The semiconductor apparatus of claim 22 , wherein a signal to control the sense amplifier and a signal to control the precharge unit are generated from a column decoder block.
24. The semiconductor apparatus of claim 23 , wherein the signal to control the sense amplifier and the signal to control the precharge unit are driven in a circuit area between a plurality of memory blocks.
25. The semiconductor apparatus of claim 22 , wherein the precharge unit is configured to precharge the first and second data I/O lines to a core voltage level.
26. A sense amplifier comprising a hybrid data transfer unit which differentially amplifies first data I/O lines in a read operation and a write operation,
wherein the first data I/O lines are coupled to the second data I/O line continuously during an active operation.
27. The sense amplifier of claim 26 , wherein the hybrid data transfer unit is configured to differentially amplify the first data I/O lines in response to a sense amplifier enable signal generated from a read command or a write command.
28. The sense amplifier of claim 26 , wherein the sense amplifier enable signal is generated from a column decoder block.
29. The sense amplifier of claim 26 , wherein the sense amplifier enable signal is driven in a circuit area between a plurality of memory blocks.
30. A semiconductor apparatus having memory blocks having memory cells capable of storing data therein, wherein the stored data are accessible via bit lines, the semiconductor apparatus comprising:
first data I/O lines connected to the bit lines;
second data I/O lines;
a sense amplifier capable of connecting the first data lines to the second data lines continuously during an active operation period.
31. The semiconductor apparatus of claim 30 , wherein the data from the memory cells are transferable to the second data I/O lines, and wherein the data on the second data I/O lines are transferable to the memory cells.
32. The semiconductor apparatus of claim 31 , wherein the sense amplifier comprises:
a hybrid data transfer unit configured to differentially amplify a data signal on the first data I/O lines; and
a data line connecting unit configured to connect the first data I/O lines and the second data I/O lines.
33. The semiconductor apparatus of claim 32 , wherein an I/O switch signal is provided to the hybrid data transfer unit and the data line connecting unit during the active operation period so as to couple the first data I/O lines and the second data I/O lines continuously during the active operation period.
34. The semiconductor apparatus of claim 33 , wherein an sense amplifier driving signal is provided to the hybrid data transfer unit to differentially amplify the first data I/O lines during the active operation period.
35. The semiconductor apparatus of claim 33 , wherein the I/O switch signal is generated from an active signal provided from an external source including a controller or a row selection signal.