Semiconductor device having plural semiconductor chips laminated to each other
In a stacked semiconductor device in which a plurality of through silicon vias used for data transfer are shared among a plurality of semiconductor chips, a first semiconductor chip included in the semiconductor chips holds through silicon via switching information for specifying a through silicon via among the through silicon vias to be used for data transfer, and transfers the through silicon via switching information to a second semiconductor chip included in the semiconductor chips. According to the present invention, because the through silicon via switching information is transferred from the first semiconductor chip to the second semiconductor chip, a circuit for storing the through silicon via switching information in a nonvolatile manner is not required in the second semiconductor chip. With this arrangement, a chip area of the second semiconductor chip can be reduced.
1. A semiconductor device comprising:
a plurality of semiconductor chips laminated to each other, the semiconductor chips including at least first and second semiconductor chips; and
a plurality of through silicon vias electrically connected in common to the plurality of semiconductor chips,
wherein the first semiconductor chip stores switching information that specifies one or more of the penetration electrodes to be used for data transfer, and the first semiconductor chip transfers the switching information to the second semiconductor chip,
wherein the first semiconductor chip includes a first switching circuit that selects one or more of the penetration electrodes to be used for data transfer based on the switching information, and the second semiconductor chip includes a second switching circuit that selects one or more of the penetration electrodes to be used for the data transfer based on the switching information transferred from the first semiconductor chip, and
wherein each of the penetration electrodes selected by the first switching circuit is electrically connected to an associated one of the penetration electrodes selected by the second switching circuit.
2. The semiconductor device as claimed in claim 1 , wherein a penetration electrode not selected by the first switching circuit is not selected by the second switching circuit either.
3. A semiconductor device comprising:
a plurality of semiconductor chips laminated to each other, the semiconductor chips including at least first and second semiconductor chips; and
a plurality of through silicon vias electrically connected in common to the plurality of semiconductor chips,
wherein the first semiconductor chip stores switching information that specifies one or more of the penetration electrodes to be used for data transfer, and the first semiconductor chip transfers the switching information to the second semiconductor chip,
wherein the first semiconductor chip includes a first switching circuit that selects one or more of the penetration electrodes to be used for data transfer based on the switching information, and the second semiconductor chip includes a second switching circuit that selects one or more of the penetration electrodes to be used for the data transfer based on the switching information transferred from the first semiconductor chip,
wherein the first semiconductor chip further includes:
a switching information storing circuit that stores the switching information; and
a parallel-to-serial converting circuit that converts the switching information read from the switching information storing circuit from parallel to serial and transfers the switching information in serial to the second semiconductor chip, and
wherein the first semiconductor chip further includes a first counter circuit that performs a counting operation in synchronization with a clock signal and a first decoder that decodes a count value of the first counter circuit, and the parallel-to-serial converting circuit performs a parallel-to-serial conversion based on an output signal of the first decoder.
4. The semiconductor device as claimed in claim 3 , wherein the second semiconductor chip includes a relief data latch circuit that latches and converts the switching information supplied in serial to parallel, and supplies the switching information in parallel to the second switching circuit.
5. The semiconductor device as claimed in claim 4 , wherein
the second semiconductor chip further includes a second counter circuit that performs a counting operation in synchronization with the clock signal and a second decoder that decodes a count value of the second counter circuit, and
the relief data latch circuit performs a latching operation based on an output signal of the second decoder.
6. The semiconductor device as claimed in claim 1 , wherein
the first switching circuit includes 1 st to n th first buffer circuits,
the second switching circuit includes 1 st to n th second buffer circuits,
the plurality of penetration electrodes includes 1 St to n+m th penetration electrodes,
the first switching circuit selectively connects each of the 1 st to n th first buffer circuits to different ones of the 1 st to n+m th penetration electrodes based on the switching information by connecting an i th first switching circuit to one of i th to i+m th penetration electrodes, where i is an integer among 1 to n, and
the second switching circuit selectively connects each of the 1 st to n th second buffer circuits to different ones of the 1 st to n+m th penetration electrodes based on the switching information by connecting an i th second switching circuit to one of i th to i+m th penetration electrodes.
7. The semiconductor device as claimed in claim 6 , wherein
the first switching circuit further includes a plurality of first tri-state buffers provided between the i th first switching circuit and each of the i th to i+m th penetration electrodes,
the second switching circuit further includes a plurality of second tri-state buffers provided between the i th second switching circuit and each of the i th to i+m th penetration electrodes,
the first switching circuit activates one of the first tri-state buffers provided between the i th first switching circuit and the i th to i+m th penetration electrodes based on the switching information, and
the second switching circuit activates one of the second tri-state buffers provided between the i th second switching circuit and the i th to i+m th penetration electrodes based on the switching information.
8. A semiconductor device comprising:
a first semiconductor chip that includes 1 st to n th first buffer circuits;
a second semiconductor chip stacked on the first semiconductor chip, and including 1 st to n th second buffer circuits;
1 st to n+m th first penetration electrodes provided in the first semiconductor chip or the second semiconductor chip; and
at least one second penetration electrode provided in the first semiconductor chip or the second semiconductor chip, wherein
the first semiconductor chip includes a switching information storing circuit that stores switching information for specifying n units of first penetration electrodes among the 1 st to n+m th first penetration electrodes and a first switching circuit that connects each of specified n units of the first penetration electrodes to an associated one of the 1 st to n th first buffer circuits based on the switching information, and
the second semiconductor chip includes a second switching circuit that connects each of specified n units of the first penetration electrodes to an associated one of the 1 st to n th second buffer circuits based on the switching information transferred from the switching information storing circuit via the second penetration electrode.
9. The semiconductor device as claimed in claim 8 , wherein
the first semiconductor chip further includes a parallel-to-serial converting circuit that converts the switching information read from the switching information storing circuit from parallel to serial, and
the switching information is transferred in serial to the second semiconductor chip via the second penetration electrode.
10. The semiconductor device as claimed in claim 8 , wherein
a plurality of the second penetration electrodes that are connected in parallel are provided, and
the switching information is transferred from the first semiconductor chip to the second semiconductor chip vias connected in parallel.
11. The semiconductor device as claimed in claim 8 , wherein
the first switching circuit selectively connects each of the 1 st to n th first buffer circuits to different ones of the 1 st to n+m th penetration electrodes based on the switching information by connecting an i th first switching circuit to one of i th to i+m th penetration electrodes, where i is an integer among 1 to n, and
the second switching circuit selectively connects each of the 1 st to n th second buffer circuits to different ones of the 1 st to n+m th penetration electrodes based on the switching information by connecting an i th second switching circuit to one of i th to i+m th penetration electrodes.
12. The semiconductor device as claimed in claim 11 , wherein
the first switching circuit further includes a plurality of first tri-state buffers provided between the i th first switching circuit and each of the i th to i+m th penetration electrodes,
the second switching circuit further includes a plurality of second tri-state buffers provided between the i th second switching circuit and each of the i th to i+m th penetration electrodes,
the first switching circuit activates one of the first tri-state buffers provided between the i th first switching circuit and the i th to i+m th through silicon vias based on the switching information, and
the second switching circuit activates one of the second tri-state buffers provided between the i th second switching circuit and the i th to i+m th penetration electrodes based on the switching information.
13. The semiconductor device as claimed in claim 8 , wherein
a plurality of the second semiconductor chips are provided,
the first penetration electrodes and the second penetration electrode are provided on each of the second semiconductor chips, and
the penetration electrodes provided on each of the second semiconductor chips are electrically connected to corresponding ones of the penetration electrodes provided on other of the second semiconductor chips.
14. A semiconductor device comprising:
a first semiconductor chip, which comprises,
a semiconductor substrate comprising a first main surface and a second main surface opposite to the first main surface,
a plurality of penetration electrodes each penetrating the semiconductor substrate from the first main surface to the second main surface and including a first end portion on a side of the first main surface and a second end portion on a side of the second main surface,
a plurality of first buffer circuits formed on the side of the second main surface,
a first switch circuit formed on the side of the second main surface, the first switch circuit being provided between the second end portions of the penetration electrodes and the first buffer circuits, and
a second semiconductor chip mounted on the side of first main surface of the semiconductor substrate of the first semiconductor chip, which comprises,
a plurality of second buffer circuits provided correspondingly to the first buffer circuits such that each of the second buffer circuits drives a signal which is driven by an associated one of the first buffer circuits,
a second switch circuit provided between the first end portions of the penetration electrodes and the second buffer circuits, and
the first and second switch circuits being controlled in common by a switch signal to select ones of the penetration electrodes to make electrical paths each formed between the one of the first buffer circuits and the associated one of the second buffer circuits.
15. The semiconductor device as claimed in claim 14 , wherein the first semiconductor chip further comprises an additional penetration electrode penetrating the semiconductor substrate from the first main surface to the second main surface, and the switch signal being transferred to the second switch circuit of the second semiconductor chip by way of the additional penetration electrode.
16. The semiconductor device as claimed in claim 14 , wherein the first and second switch circuit are controlled in common by the switch signal to make non-selected one or ones of the penetration electrodes high impedance.
17. The semiconductor device as claimed in claim 15 , wherein the second switch circuit includes a first circuit portion controlled by a first control bit of the switch signal and a second circuit portion controlled by a second control bit of the switch signal, the first and second control bits of the switch signal being transferred in series through the additional penetration electrode.
18. The semiconductor device as claimed in claim 17 , wherein the second semiconductor chip includes a serial-to-parallel conversion circuit electrically coupled to the additional penetration electrode of the first semiconductor chip, the serial-to-parallel conversion circuit receiving the first and second control bits in series and outputting the first and second control bits in parallel to the second switch circuit.
19. The semiconductor device as claimed in claim 15 , wherein the first semiconductor chip further comprises another additional penetration electrode penetrating the semiconductor substrate from the first main surface to the second main surface, the switch signal being transferred to the second switch circuit of the second semiconductor chip by way of a parallel electrical path formed by the additional penetration electrode and the another additional penetration electrode.