Metallization and its use in, in particular, an IGBT or a diode

1. A method for fabricating a power semiconductor component having a semiconductor body having at least two main surfaces, the method comprising:

a) applying a layer of a metallization on at least one of the main surfaces, the layer having a thickness of at least 15 μm, the layer serving as a heat sink; and

b) producing a field stop zone in the semiconductor body by implantation of protons or helium through the layer.

2. The method as claimed in claim 1 , wherein the semiconductor body has a front side and a rear side, and wherein step b) further comprises effecting the implantation from one of the rear side or the front side.

3. The method as claimed in claim 1 , further comprising: c) performing a heat treatment on at least a portion of the power semiconductor component subsequent to step b).

4. The method as claimed in claim 3 , wherein step c) further comprises performing the heat treatment in the range of 350° C. to 450° C.

5. The method as claimed in claim 3 , wherein step b) further comprises using the layer for masking for the implantation, the implantation occurring from a front side of the semiconductor body.

6. The method as claimed in claim 5 , wherein step c) further comprises performing the heat treatment at approximately between 220° C. and 350° C.

7. The method as claimed in claim 1 , wherein step a) further comprises applying the layer such that the layer has a specific heat capacity per volume that is at least a factor of 1.3 higher than the specific heat capacity per volume of the semiconductor body, and the specific thermal conductivity of the layer is greater than that of the semiconductor body.

8. The method as claimed in claim 7 , wherein step a) further comprises applying the layer directly to the at least one main surface.

9. The method as claimed in claim 7 , wherein step a) further comprises applying the layer via a diffusion barrier layer to the at least one main surface.

10. The method as claimed in claim 9 , wherein the diffusion barrier layer is formed from at least one of the group consisting of Ti, TiN, Ta, TaN and Al.

11. The method as claimed in claim 10 , wherein the diffusion barrier layer is formed by a first sublayer composed of Ti/TiN or Ta/TaN, and a second sublayer composed of Al.

12. The method as claimed in claim 7 , wherein step a) further comprises applying the layer such that the layer has a layer thickness of 20 to 60 μm.

13. The method as claimed in claim 7 , further comprising a step of subsequently reinforcing the layer using additional heat sinks.

14. The method as claimed in claim 1 , wherein step a) further comprises applying the layer such that the thermal capacity of the layer is at least 10% of the thermal capacity of the semiconductor body.

15. The method as claimed in claim 14 , wherein step a) further comprises applying the layer such that the layer has a thermal capacity having a magnitude at least equal to half the thermal capacity of the semiconductor chip.

16. The method as claimed in claim 1 , wherein step a) further comprises applying the layer to at least the main surface of the semiconductor body that forms the rear side of the semiconductor body.

17. The method as claimed in claim 1 , wherein the layer is formed from at least one of the group consisting of copper, aluminum, silver and gold.

18. The method as claimed in claim 1 , wherein step a) further comprises applying the layer such that the layer has a layer thickness of approximately 50 μm.

19. The method as claimed in claim 1 , wherein step a) further comprises electrodepositing the layer or depositing the layer by vapor deposition.