A/D converter with compressed full-scale range
An embodiment of an analog-to-digital converter system is described wherein an analog voltage signal Vin(t) is provided by an input amplifier. The analog signal Vin(t) has a predetermined full-scale range that is less wide than a reference voltage (Vref) range used by a downstream ADC to derive a first digital (numerical) representation D 1 ( k ) of a sampled value Vin(k) of the analog signal Vin(t). The first digital representation has N bits. A digital circuit then converts the N-bit D 1 ( k ) code to a second numerical representation D 2 ( k ) of the sampled analog voltage Vin(k) with respect to the full-scale range of the ADC system. The D 2 ( k ) code has P bits of resolution, which may be less than N bits. The P-bit D 2 ( k ) code representing Vin(k) is the output of the ADC system. Therefore, the width of the reference voltage range applied to the ADC is greater than the width of the system's full-scale range at the output of the system.
1. An analog-to-digital converter system comprising:
a generator circuit configured to generate a digital dither code selected from a sequence of digital dither codes that is at least pseudo random;
a first circuit for offsetting a sampled analog voltage using the digital dither code;
a first analog-to-digital converter configured to provide a first digital code representing the sampled analog voltage with an offset induced by the digital dither code;
a combiner configured to combine the first digital code and the digital dither code to substantially cancel the offsetting of the sampled analog voltage, the combiner providing a first numerical representation of the sampled analog voltage with respect to a reference voltage range; and
a digital circuit configured to scale and truncate the first numerical representation to derive a second numerical representation of the sampled analog voltage with respect to a full-scale range of the analog-to-digital converter system,
wherein a width of the reference voltage range is greater than a width of the full-scale range, and
wherein a least significant bit size of the first numerical representation is smaller than a least significant bit size of the second numerical representation.
2. The analog-to-digital converter system of claim 1 wherein the first analog-to-digital converter and the digital circuit are implemented on a single semiconductor die.
3. The analog-to-digital converter system of claim 1 wherein the least significant bit size of the first numerical representation is equal to a least significant bit size of the digital dither code.
4. The analog-to-digital converter system of claim 3 wherein a least significant bit size of the first digital code is larger than the least significant bit size of the first numerical representation.
5. The analog-to-digital converter system of claim 1 wherein the digital circuit is configured to implement a truth table defining a scaling-and-limiting operation.
6. The analog-to-digital converter system of claim 4 wherein the first analog-to-digital converter derives the first digital code by successive approximation in a first number of bit test cycles that is less than a second number of bits in the first numerical representation of the sampled analog voltage.
7. The analog-to-digital converter system of claim 1 wherein the first analog-to-digital converter derives the first digital code by successive approximation in a first number of bit test cycles that is less than a second number of bits in the first numerical representation of the sampled analog voltage.
8. The analog-to-digital converter system of claim 7 further comprising an active circuit providing an analog voltage signal being sampled to derive the sampled analog voltage, the active circuit having a power supply terminal substantially biased at a first reference voltage potential delimiting the reference voltage range.
9. The analog-to-digital converter system of claim 7 further comprising an active circuit providing an analog voltage signal being sampled to derive the sampled analog voltage, the active circuit and the first analog-to-digital converter being powered by a two-terminal power source.
10. The analog-to-digital converter system of claim 1 wherein the digital circuit is configured to scale the first numerical representation of the sampled voltage by a non-integer multiplication factor.
11. The analog-to-digital converter system of claim 1 wherein a saturation limit of the first numerical representation is the same as a saturation limit of the second numerical representation.
12. The analog-to-digital converter system of claim 1 wherein the digital circuit is programmable and the full-scale range is selected by programming from a plurality of selectable full-scale ranges.
13. The analog-to-digital converter system of claim 12 wherein the plurality of selectable full-scale ranges includes a second full-scale range substantially equal to the reference voltage range.
14. The analog-to-digital converter system of claim 1 further comprising a digital-to-analog converter configured to receive the digital dither code.
15. The analog-to-digital converter system of claim 14 wherein an output of the digital-to-analog converter is combined with the sampled analog voltage to induce the offset in the first digital code.
16. The analog-to-digital converter system of claim 1 wherein the digital circuit is configured to scale the first numerical representation by a factor of five quarters.
17. The analog-to-digital converter system of claim 1 wherein the width of the full-scale range is eighty percent of the width of the reference voltage range.
18. The analog-to-digital converter system of claim 1 wherein the first analog-to-digital converter derives the first digital code by successive approximation in a first number of bit test cycles, wherein
the first number of bit test cycles is less than a second number of bits in the first numerical representation of the sampled analog voltage, and
the first number of bit test cycles is equal to or greater than a third number of bits in the second numerical representation of the sampled analog voltage.
19. The analog-to-digital converter system of claim 1 wherein the generator circuit comprises a cellular-automata-shift-register circuit configured to provide a pseudo random sequence.
20. The analog-to-digital converter system of claim 1 wherein the generator circuit comprises a linear-feedback-shift-register circuit configured to provide a pseudo random sequence.