Methods of forming a memory array with a pair of memory-cell strings to a single conductive pillar

1. A method of forming a memory array, comprising:

forming a source line;

forming a first string of serially-coupled memory cells on a first side of at least one conductive pillar and over the source line;

forming a second string of serially-coupled memory cells on a second side of the at least one conductive pillar and over the source line;

forming a data line over the first string of serially-coupled memory cells and the second string of serially-coupled memory cells; and

forming a single select transistor so that the single select transistor selectively couples the first string of serially-coupled memory cells on the first side of at least one conductive pillar to the source line and so that the single select transistor also selectively couples the second string of serially-coupled memory cells on the second side of the at least one conductive pillar to the source line;

wherein forming the first string of memory cells comprises forming at least a first control gate on the first side of the at least one conductive pillar and interposing at least a first charge trap between the first side of the at least one conductive pillar and the first control gate;

wherein forming the second string of memory cells comprises forming at least a second control gate on the second side of the at least one conductive pillar and interposing at least a second charge trap between the second side of the at least one conductive pillar and the second control gate; and

wherein the first and second charge traps are electrically isolated from each other and the first and second control gates are electrically isolated from each other.

2. The method of claim 1 , further comprising forming an isolation region between the first and second control gates.

3. The method of claim 2 , wherein forming the isolation region comprises forming a slot through at least one conductive layer and at least a portion of a charge trapping layer, and filling the slot with a dielectric material, wherein the control gates are formed from the at least one conductive layer and the charge traps are formed from the charge trapping layer.

4. The method of claim 3 , wherein forming the slot through the at least a portion of the charge trapping layer comprises forming the slot through an oxide layer and a nitride layer.

5. The method of claim 4 , wherein forming the slot through the at least a portion of the charge trapping layer further comprises forming the slot through an other oxide layer.

6. The method of claim 5 , wherein the oxide layers and the nitride layers are deposited using low pressure chemical vapor deposition.

7. The method of claim 1 , wherein the single select gate selectively couples the at least one conductive pillar to the source line.

8. The method of claim 1 , wherein the single select transistor is a first single select transistor, and further comprising forming a second single select transistor so that the second single select transistor selectively couples the first string of serially-coupled memory cells on the first side of at least one conductive pillar to the data line and so that the second single select transistor also selectively couples the second string of serially-coupled memory cells on the second side of the at least one conductive pillar to the data line.

9. The method of claim 8 , wherein the at least one conductive pillar on which the first and second strings of serially-coupled of memory cells are formed is a first conductive pillar, and wherein forming the first single select transistor comprises forming the first single select transistor on a second conductive pillar and forming the second single select transistor comprises forming the second single select transistor on a third conductive pillar.

10. The method of claim 9 , further comprising coupling the second conductive pillar to the data line and coupling the first conductive pillar and the third conductive pillar to the source line and the first conductive pillar.

11. The method of claim 8 , wherein the second single select transistor selectively couples the at least one conductive pillar to the data line.

12. The method of claim 9 , wherein forming the first single select transistor on the second conductive pillar comprises forming a control gate of the first single select transistor on the second conductive pillar and interposing a gate dielectric of the first single select transistor between the second conductive pillar and the control gate of the first single select transistor, and wherein forming the second single select transistor on the third conductive pillar comprises forming a control gate of the second single select transistor on the third conductive pillar and interposing a gate dielectric of the second single select transistor between the third conductive pillar and the control gate of the second single select transistor.

13. A method of forming a memory array, comprising:

forming a first conductive layer over a substrate;

forming at least a second conductive layer over the first conductive layer;

forming one or more holes through each of the conductive layers, each hole exposing a portion of each conductive layer;

forming a charge trapping layer within each hole on the exposed portion of the first conductive layer and on the exposed portion of the second conductive layer;

forming a conductive pillar within each hole, wherein the charge trapping layer is interposed between the conductive pillar and the exposed portion of the first conductive layer and between the conductive pillar and the exposed portion of the second conductive layer; and

cutting the charge trapping layer with an isolation region to form a pair of isolated memory cells, wherein a first memory cell of the pair of isolated memory cells forms a portion of a first string of series-coupled memory cells on a first side of the conductive pillar and wherein a second memory cell of the pair of isolated memory cells forms a portion of a second string of series-coupled memory cells on a second side of the conductive pillar; and

forming a single select transistor so that the single select transistor selectively couples the first string of serially-coupled memory cells on the first side of the conductive pillar to a source line and so that the single select transistor also selectively couples the second string of serially-coupled memory cells on the second side of the conductive pillar to the source line.

14. The method of claim 13 , further comprising forming a dielectric over the first conductive layer before forming the at least the second conductive layer, wherein the dielectric is between the first conductive layer and the at least the second conductive layer.

15. The method of claim 13 , wherein the single select transistor is a first single select transistor, and further comprising forming a second single select transistor so that the second single select transistor selectively couples the first string of serially-coupled memory cells on the first side of the conductive pillar to a data line and so that the second single select transistor also selectively couples the second string of serially-coupled memory cells on the second side of the conductive pillar to the data line.

16. A method of forming a memory array, comprising:

forming a first conductive layer over a substrate;

forming at least a second conductive layer over the first conductive layer;

forming one or more holes through each of the conductive layers, each hole exposing a portion of each conductive layer;

forming a charge trapping layer within each hole on the exposed portion of the first conductive layer and on the exposed portion of the second conductive layer;

forming a conductive pillar within each hole, wherein the charge trapping layer is interposed between the conductive pillar and the exposed portion of the first conductive layer and between the conductive pillar and the exposed portion of the second conductive layer; and

cutting the charge trapping layer with an isolation region to form a pair of isolated memory cells;

wherein cutting the charge trapping layer with the isolation region further cuts the first conductive layer into isolated first and second control gates.

17. The method of claim 16 , wherein cutting the first conductive layer into isolated first and second control gates comprises cutting the first conductive layer into isolated control gates of a first and second memory cell of the pair of isolated memory cells.

18. A method of forming a memory array, comprising:

forming a first conductive layer over a substrate;

forming one or more first holes through the first conductive layer each first hole exposing a portion of the first conductive layer;

forming a first dielectric within each first hole on the exposed portion of the first conductive layer;

forming a first conductive pillar within each first hole, wherein the first dielectric is interposed between the first conductive pillar and the exposed portion of the first conductive layer and wherein the first conductive layer forms a control gate of a first select transistor;

forming a second conductive layer over the first conductive layer;

forming at least a third conductive layer over the second conductive layer;

forming one or more second holes through each of the second and third conductive layers, each hole exposing a portion of each of the second and third conductive layers;

forming a charge trapping layer within each second hole on the exposed portion of the second conductive layer and on the exposed portion of the third conductive layer;

forming a second conductive pillar within each second hole, wherein the charge trapping layer is interposed between the second conductive pillar and the exposed portion of the second conductive layer and between the second conductive pillar and the exposed portion of the third conductive layer;

cutting the charge trapping layer with an isolation region to form a pair of isolated memory cells;

forming a fourth conductive layer over the at least the third conductive layer;

forming one or more third holes through the fourth conductive layer each third hole exposing a portion of the fourth conductive layer;

forming a second dielectric within each third hole on the exposed portion of the fourth conductive layer; and

forming a third conductive pillar within each third hole, wherein the second dielectric is interposed between the third conductive pillar and the exposed portion of the fourth conductive layer and wherein the fourth conductive layer forms a control gate of a second select transistor.

19. The method of claim 18 , wherein each second conductive pillar is between and is coupled to respective ones of the first and third conductive pillars.

20. The method of claim 19 , further comprising forming a fifth conductive layer over the third conductive pillars, wherein the fifth conductive layer is coupled to the third conductive pillars.

21. The method of claim 20 , further comprising conductively doping the substrate and coupling the substrate to the first conductive pillars.

22. The method of claim 18 , wherein the pair of isolated memory cells is a first pair of isolated memory cells, wherein cutting the charge trapping layer with the isolation region further forms a second pair of isolated memory cells, wherein cutting the charge trapping layer with the isolation region further cuts the second conductive layer into isolated first and second control gates respectively of first and second memory cells of the first pair of isolated memory cells and the at least the third conductive layer into isolated first and second control gates respectively of first and second memory cells of the second pair of isolated memory cells, wherein the first memory cells of the first and second pairs of isolated memory cells are coupled in series, and wherein the second memory cells of the first and second pairs of isolated memory cells are coupled in series.