Wafer level packaging
View Patent ↗A method of wafer level packaging includes providing a substrate including a buried oxide layer and a top oxide layer, and etching the substrate to form openings above the buried oxide layer and a micro-electro-mechanical systems (MEMS) resonator element between the openings, the MEMS resonator element enclosed within the buried oxide layer, the top oxide layer, and sidewall oxide layers. The method further includes filling the openings with polysilicon to form polysilicon electrodes adjacent the MEMS resonator element, removing the top oxide layer and the sidewall oxide layers adjacent the MEMS resonator element, bonding the polysilicon electrodes to one of a complementary metal-oxide semiconductor (CMOS) wafer or a carrier wafer, removing the buried oxide layer adjacent the MEMS resonator element, and bonding the substrate to a capping wafer to seal the MEMS resonator element between the capping wafer and one of the CMOS wafer or the carrier wafer.
1. A method, comprising:
providing a substrate including a buried oxide layer and a top oxide layer;
etching the substrate to form openings above the buried oxide layer and a micro-electro-mechanical systems (MEMS) resonator element between the openings, the MEMS resonator element enclosed within the buried oxide layer, the top oxide layer, and sidewall oxide layers;
filling the openings with polysilicon to form polysilicon electrodes adjacent the MEMS resonator element;
removing the top oxide layer and the sidewall oxide layers adjacent the MEMS resonator element;
bonding the polysilicon electrodes to one of a complementary metal-oxide semiconductor (CMOS) wafer or a carrier wafer;
removing the buried oxide layer adjacent the MEMS resonator element; and
bonding the substrate to a capping wafer to seal the MEMS resonator element between the capping wafer and one of the CMOS wafer or the carrier wafer.
2. The method of claim 1 , wherein the polysilicon electrodes are each formed to have an “L” shape.
3. The method of claim 1 , wherein bonding the polysilicon electrodes to one of the CMOS wafer or the carrier wafer includes fusion bonding at a temperature less than about 480 degrees Celsius.
4. The method of claim 1 , wherein bonding the substrate to the capping wafer includes eutectic bonding with a bonding force greater than about 15 kN at a temperature greater than about 400 degrees Celsius.
5. The method of claim 1 , further comprising electrically coupling the polysilicon electrodes to a metal layer of the CMOS wafer.
6. The method of claim 1 , further comprising electrically coupling the polysilicon electrodes to a metal layer of the CMOS wafer with respective tungsten plugs disposed between the polysilicon electrodes and the metal layer.
7. The method of claim 1 , further comprising:
etching one of the polysilicon electrodes and the substrate to form an aperture above the buried oxide layer; and
depositing and patterning an aluminum nitride (AlN) film over the aperture.
8. The method of claim 1 , further comprising:
etching one of the polysilicon electrodes to form an aperture above the substrate;
depositing and patterning an aluminum nitride (AlN) film over the aperture; and
depositing and patterning an aluminum film above the AlN film.
9. A method, comprising:
providing a substrate including a buried oxide layer and a top oxide layer;
etching the substrate to form openings above the buried oxide layer and a micro-electro-mechanical systems (MEMS) resonator element between the openings, the MEMS resonator element enclosed within the buried oxide layer, the top oxide layer, and sidewall oxide layers;
filling the openings with polysilicon to form polysilicon electrodes adjacent the MEMS resonator element;
removing the top oxide layer and the sidewall oxide layers adjacent the MEMS resonator element;
fusion bonding the polysilicon electrodes to a complementary metal-oxide semiconductor (CMOS) wafer;
electrically coupling the polysilicon electrodes to a metal layer of the CMOS wafer with respective plugs;
removing the buried oxide layer adjacent the MEMS resonator element; and
eutectic bonding the substrate to a capping wafer to seal the MEMS resonator element between the capping wafer and the CMOS wafer.
10. The method of claim 9 , wherein the polysilicon electrodes are each formed to have an “L” shape.
11. The method of claim 9 , wherein the fusion bonding occurs at a temperature less than about 480 degrees Celsius.
12. The method of claim 9 , wherein the eutectic bonding occurs with a bonding force greater than about 15 kN at a temperature greater than about 400 degrees Celsius.
13. The method of claim 9 , further comprising electrically coupling the polysilicon electrodes to the metal layer of the CMOS wafer with respective tungsten plugs disposed between the polysilicon electrodes and the metal layer.
14. The method of claim 9 , further comprising:
etching one of the polysilicon electrodes and the substrate to form an aperture above the buried oxide layer; and
depositing and patterning an aluminum nitride (AlN) film over the aperture.
15. The method of claim 9 , further comprising:
etching one of the polysilicon electrodes to form an aperture above the substrate;
depositing and patterning an aluminum nitride (AlN) film over the aperture; and
depositing and patterning an aluminum film above the AlN film.