Common air interface supporting single carrier and OFDM

1. A matched filter configured to match an input signal to at least one of a set of programmable-length complementary Golay-code pairs, comprising:

a sequence of delay elements configured for generating at least one sequence of delays represented by at least one delay vector, and delaying at least the input signal by the at least one sequence of delays, and

a sequence of programmable seed vector insertion elements configured for multiplying at least the input signal by at least one of a plurality of seed-vector values, the sequence of programmable seed vector insertion elements further configured for setting at least one of the plurality of seed-vector values to zero.

2. The matched filter recited in claim 1 , configured for matching the input signal to complementary Golay-code pairs having a plurality of code lengths.

3. The matched filter recited in claim 1 , wherein the sequence of programmable seed vector insertion elements is configured for generating a combination of binary and complex symbols.

4. The matched filter recited in claim 1 , wherein the at least one delay vector comprises a single set of delays for matching the input signal to a plurality of complementary Golay-code pairs.

5. The matched filter recited in claim 1 , wherein the sequence of programmable seed vector insertion elements is configured for generating seed-vector values corresponding to complementary Golay-code pairs for each of a plurality of piconets.

6. The matched filter recited in claim 1 , wherein the at least one delay vector comprises a plurality of compatible delay vectors.

7. The matched filter recited in claim 1 , further configured to decode a first frame portion having a first Golay code length and configured to decode a second frame portion having a second Golay code length, the second Golay code length being different from the first Golay code length.

8. A matched filtering method for matching an input signal to at least one of a set of programmable-length complementary Golay-code pairs, comprising:

delaying at least the input signal with a sequence of delays,

generating a plurality of seed-vector values, wherein at least one of the plurality of seed-vector values is set to zero, and

multiplying at least the input signal by at least one of a plurality of programmable seed-vector values.

9. The method recited in claim 8 , further comprising matching the input signal to complementary Golay-code pairs having a plurality of code lengths.

10. The method recited in claim 8 , wherein generating a plurality of seed-vector values comprises generating a combination of binary and complex symbols.

11. The method recited in claim 8 , wherein delaying comprises providing a single set of delays for matching the input signal to a plurality of complementary Golay-code pairs.

12. The method recited in claim 8 , wherein generating a plurality of seed-vector values comprises generating seed-vector values corresponding to complementary Golay-code pairs for each of a plurality of piconets.

13. The method recited in claim 8 , wherein delaying comprises generating a plurality of compatible delay vectors.

14. The method recited in claim 8 , further comprising decoding a first frame portion having a first Golay code length and decoding a second frame portion having a second Golay code length, the second Golay code length being different from the first Golay code length.

15. A digital computer system programmed to perform the method recited in claim 8 .

16. A matched-filtering system configured for matching an input signal to at least one of a set of programmable-length complementary Golay-code pairs, comprising:

a delay means configured for generating at least one sequence of delays represented by at least one delay vector, and delaying at least the input signal by the at least one sequence of delays, and

a programmable seed vector insertion means configured for multiplying at least the input signal by at least one of a plurality of seed-vector values, wherein the programmable seed vector insertion means comprises a seed-vector generation means configured for setting at least one of the plurality of seed-vector values to zero.

17. The system recited in claim 16 , further configured for matching the input signal to complementary Golay-code pairs having a plurality of code lengths.

18. The system recited in claim 16 , wherein the programmable seed vector insertion means is configured for generating a combination of binary and complex symbols.

19. The system recited in claim 16 , wherein the at least one delay vector comprises a single set of delays for matching the input signal to a plurality of complementary Golay-code pairs.

20. The system recited in claim 16 , wherein the programmable seed vector insertion means is configured for generating seed-vector values corresponding to complementary Golay-code pairs for each of a plurality of piconets.

21. The system recited in claim 16 , wherein the at least one delay vector comprises a plurality of compatible delay vectors.

22. The system recited in claim 16 , further configured to decode a first frame portion having a first Golay code length and configured to decode a second frame portion having a second Golay code length, the second Golay code length being different from the first Golay code length.

23. A computer-program product for matching an input signal to at least one of a set of programmable-length complementary Golay-code pairs, comprising:

computer-readable device comprising codes executable by at least one computer to: delay at least the input signal with a sequence of delays,

generate a plurality of seed-vector values, wherein at least one of the plurality of seed-vector values is set to zero, and

multiply at least the input signal by at least one of a plurality of programmable seed-vector values.