Signal calibration methods and apparatuses
In a signal calibration scheme, a desired phase relationship is maintained between a set of signals. For example, in some aspects the desired phase of a clock tree generated from a high speed reference clock signal may be maintained by detecting phase differences between a low speed reference clock signal and low speed clock signals associated with different phases of the clock tree. In some aspects, the desired phase of a clock tree may be maintained by detecting framing offsets that occur through the use of the clock tree.
1. A method of signal calibration, comprising:
receiving a first clock signal having a first nominal frequency;
receiving a second clock signal having a second nominal frequency that is a divisor of the first nominal frequency;
generating a plurality of clock signals based on the first clock signal, wherein the generated clocks signals include a third clock signal having the second nominal frequency;
determining a phase difference between the second clock signal and the third clock signal; and
selecting, based on the phase difference, one subset of a plurality of subsets of the generated clock signals.
2. The method of claim 1 , wherein the subsets define different clock phase relationships.
3. The method of claim 1 , wherein, if the phase difference is less than or equal to a defined skew tolerance, the selected subset is a subset that includes the third clock signal.
4. The method of claim 1 , wherein, if the phase difference is greater than or equal to a defined skew tolerance, the selected subset is a subset that does not include the third clock signal.
5. The method of claim 1 , wherein the plurality of clock signals have frequencies that are divisors of the first nominal frequency.
6. The method of claim 1 , further comprising generating a pulse if the phase difference is greater than a defined skew tolerance, wherein:
the pulse causes a counter to increment; and
the output of the counter is provided to select the one subset.
7. The method of claim 6 , wherein:
the generated clock signals are provided to inputs of at least one multiplexer; and
the output of the counter is provided to the at least one multiplexer to select the one subset.
8. The method of claim 6 , further comprising repeatedly generating the pulse to change the output of the counter until a desired one of the subsets is selected to thereby provide calibrated clock signals.
9. The method of claim 1 , wherein the plurality of clock signals are generated in a memory device to clock data into and/or out of the memory device.
10. The method of claim 9 , wherein the memory device comprises a DRAM.
11. The method of claim 9 , wherein the memory device comprises a memory module.
12. An apparatus for signal calibration, comprising:
a clock divider configured to:
receive a first clock signal having a first nominal frequency, and
generate a plurality of clock signals based on the first clock signal,
wherein the generated clocks signals include a third clock signal having a second nominal frequency that is a divisor of the first nominal frequency; and
a phase selector configured to:
receive a second clock signal having the second nominal frequency,
determine a phase difference between the second clock signal and the third clock signal, and
select, based on the phase difference, one subset of a plurality of subsets of the generated clock signals.
13. The apparatus of claim 12 , wherein the subsets define different clock phase relationships.
14. The apparatus of claim 12 , wherein the phase selector is further configured to select a subset that includes the third clock signal if the phase difference is less than a defined skew tolerance.
15. The apparatus of claim 12 , wherein the phase selector is further configured to select a subset that does not include the third clock signal if the phase difference is greater than a defined skew tolerance.
16. The apparatus of claim 12 , wherein the plurality of clock signals have frequencies that are divisors of the first nominal frequency.
17. The apparatus of claim 12 , wherein:
the phase selector is further configured to generate a pulse if the phase difference is greater than a defined skew tolerance;
the phase selector comprises a counter;
the pulse is provided to increment the counter; and
the output of the counter is provided to select the one subset.
18. The apparatus of claim 17 , wherein:
the generated clock signals are provided to inputs of at least one multiplexer of the phase selector; and
the output of the counter is provided to the at least one multiplexer to select the one subset.
19. The apparatus of claim 17 , wherein the phase selector is further configured to repeatedly generate the pulse to change the output of the counter until a desired one of the subsets is selected to thereby provide calibrated clock signals.
20. The apparatus of claim 12 , wherein:
the apparatus comprises a memory device; and
the plurality of clock signals are generated to clock data into and/or out of the memory device.
21. The apparatus of claim 20 , wherein the memory device comprises a DRAM.
22. The apparatus of claim 20 , wherein the memory device comprises a memory module.
23. An apparatus for signal calibration, comprising:
means for receiving a first clock signal having a first nominal frequency;
means for receiving a second clock signal having a second nominal frequency that is a divisor of the first nominal frequency;
means for generating a plurality of clock signals based on the first clock signal, wherein the generated clocks signals include a third clock signal having the second nominal frequency;
means for determining a phase difference between the second clock signal and the third clock signal; and
means for selecting, based on the phase difference, one subset of a plurality of subsets of the generated clock signals.