Memory accelerator buffer replacement method and system
A microcontroller using an optimized buffer replacement strategy comprises a memory configured to store instructions, a processor configured to execute said program instructions, and a memory accelerator operatively coupled between the processor and the memory. The memory accelerator is configured to receive an information request and overwrite the buffer from which the prefetch was initiated with the requested information when the request is fulfilled by a previously initiated prefetch operation.
1. A microcontroller comprising:
a memory configured to store instructions including a current instruction stream;
a processor configured to execute said instructions; and
a memory accelerator operatively coupled between the processor and the memory, the memory accelerator including a buffer containing a previous instruction from a previously initiated prefetch, the memory accelerator configured to prefetch a new instruction of the current instruction stream and to overwrite the previous instruction in said buffer with the new instruction when said prefetch of the new instruction is initiated as a result of the previously initiated prefetch and when the new instruction directly follows the previous instruction in an order defined by a prefetch scheme;
wherein the memory accelerator is configured to store said new instruction in a least recently used buffer when the previous instruction is not part of said current instruction stream.
2. The microcontroller of claim 1 , wherein a next to least recently used buffer is used to store the new instruction when the previous instruction is not part of said current instruction stream and when a least recently used buffer is about to be used.
3. The microcontroller of claim 1 , wherein the prefetch of the new instruction is fulfilled by an existing buffer when said new instruction is already in said existing buffer.
4. The microcontroller of claim 1 , wherein the processor is an Advanced RISC (Reduced Instruction Set Computer) Machine.
5. The microcontroller of claim 1 , wherein the memory is a flash memory.
6. The microcontroller of claim 1 , wherein the previous instruction belongs to the current instruction stream and wherein the new instruction is not stored in said buffer until a fetch request by the processor for the previous instruction is fulfilled.
7. The microcontroller of claim 1 , wherein the prefetch sequence defined by the prefetch scheme is given by the program order.
8. The microcontroller of claim 7 , wherein the prefetch sequence defined by the prefetch scheme is given by a branch prediction.
9. A memory accelerator comprising:
a bus interface for communicating with a processor coupled to said bus;
a memory interface for communicating with a memory, said memory including instructions;
a buffer array coupled between said bus interface and said memory interface; and
a memory accelerator control module operatively coupled to said bus interface, buffer array, and memory interface, the memory accelerator control module configured to fulfill a current prefetch operation of a current instruction stream of said instructions and to overwrite a content of a buffer of the buffer array that caused said current prefetch operation with information from said current prefetch operation only when said current prefetch operation is a result of a previously initiated prefetch operation of said current instruction stream, wherein the previously initiated prefetch operation directly precedes the current prefetch operation in a prefetch sequence defined by a prefetch scheme;
wherein the memory accelerator control module is configured to store said information in a least recently used buffer of said buffer array when no previously initiated prefetch operation of said current instruction stream is present.
10. The memory accelerator of claim 9 , wherein a next to least recently used buffer of said plurality of buffers is used when no previously initiated prefetch operation of said current instruction stream is present and when a least recently used buffer is about to be used.
11. The memory accelerator of claim 9 , wherein the prefetch operation is fulfilled by an existing buffer when said information is already in said existing buffer.
12. The memory accelerator of claim 9 , wherein the processor is an Advanced RISC (Reduced Instruction Set Computer) Machine.
13. The memory accelerator of claim 9 , wherein the memory is a flash memory.
14. A method for operating a memory system, the method comprising:
requesting a new instruction from a memory; and
storing the new instruction in a buffer array according to a buffer replacement strategy, the buffer array including a first buffer containing a previous instruction and a second buffer different from the first buffer, wherein the buffer replacement strategy includes:
a parental replacement strategy wherein, if the request for the new instruction is initiated as a result of the previous instruction and the new instruction and the previous instruction belong to a same first instruction stream, then the new instruction is stored in the first buffer and the previous instruction is overwritten with the new instruction, where the new instruction directly follows the previous instruction in an order defined by a prefetch scheme, and
a second replacement strategy wherein, if the new instruction and the previous instruction belong to different instruction streams, then the new instruction is stored in the second buffer.
15. The method of claim 14 , wherein the second replacement strategy is a least recently used strategy and the second buffer represents a least recently used buffer.
16. The method of claim 14 , wherein the first instruction stream is a prefetch operation.
17. The method of claim 14 , wherein the second replacement strategy further includes: if the previous instruction belongs to an instruction stream of a prefetch operation and the new instruction belongs to an instruction stream of an interrupt service routine, then the new instruction is stored in a least recently used buffer.