Methods and systems for N-state signal processing with binary devices
Linear Feedback Shift Registers (LFSRs) based 2 p state with p>2 or p≧2 scramblers, descramblers, sequence generators and sequence detectors in binary implementation are provided. An LFSR may apply devices implementing a binary XOR or EQUIVALENT function, a binary shift register and binary inverters and binary state generator, wherein at least an output of one shift register element in a first LFSR is connected to a device implementing a reversible binary logic function is a second LFSR. They may also apply 2 p state inverters using binary combinational logic are applied. Memory based binary 2 p state inverters are also applied. Non-LFSR based n-state scramblers and descramblers in binary logic are also provided. A method for simple correlation calculation is provided. Communication systems and data storage systems applying the provided LFSR devices are also disclosed.
1. A method for scrambling with a scrambler a sequence of p n-state symbols not generated by the scrambler with n equal to or greater than 2 and with p>1, each n-state symbol able to assume one of n states, into a sequence of p scrambled n-state symbols, comprising:
inputting an n-state symbol in the sequence of p n-state symbols on a first input of a reversible n-state logic function;
receiving on a second input of the reversible n-state logic function an n-state symbol provided by an output of an n-state shift register that is part of an n-state Linear Feedback Shift Register (LFSR) based scrambler in Galois configuration with a shift register of k n-state shift register elements with k<p;
providing on an input of the n-state shift register an n-state symbol that is available on an output of the reversible n-state logic function;
providing on a tap into the n-state shift register the n-state symbol that is available on the output of the reversible n-state logic function; and
providing an n-state symbol in the sequence of p scrambled n-state symbols on an output of the n-state Linear Feedback Shift Register (LFSR) based scrambler in Galois configuration.
2. The method of claim 1 , wherein n>2.
3. The method of claim 2 , wherein an n-state symbol is processed as a plurality of bits and the n-state shift register is realized as a plurality of binary shift registers.
4. The method of claim 3 , wherein the plurality of binary shift registers form a plurality of cross-connected binary LFSRs with a plurality of reversible binary logic functions.
5. The method of claim 2 , wherein the n-state LFSR includes at least one non-commutative n-state logic function.
6. The method of claim 1 , further comprising a self-synchronizing method of descrambling that descrambles the sequence of p scrambled n-state symbols into a sequence of p descrambled n-state symbols that is equivalent to the sequence of p n-state symbols.
7. The method of claim 1 , wherein the method is applied in a communication system.
8. The method of claim 1 , wherein the method is applied in a storage system.
9. The method of claim 1 , further comprising inverting an n-state symbol in accordance with an n-state inverter before it is provided to an input.
10. A descrambler for descrambling a sequence of p scrambled n-state symbols with n equal to or greater than 2 not generated by the descrambler, each n-state symbol able to assume one of n states, into a sequence of p descrambled n-state symbols with p>1, comprising:
an n-state Linear Forward Connected Shift Register (LFCSR) in Galois configuration having an n-state shift register with an input and an output, the input of the n-state shift register enabled to receive the sequence of p scrambled n-state symbols and the input of the n-state shift register being connected to at least one tap of the n-state LFCSR;
a first device implementing an n-state reversible logic function with a first input being connected to the output of the n-state shift register, and a second input being connected to the input of the n-state shift register; and
an output of the first device enabled to provide the sequence of p descrambled n-state symbols.
11. The descrambler of claim 10 , wherein a connection to an input includes an n-state inverter.
12. The descrambler of claim 10 , wherein n>2.
13. The descrambler of claim 12 , wherein an n-state symbol is processed as a plurality of bits and the n-state shift register is realized as a plurality of binary shift registers.
14. The descrambler of claim 13 , wherein the plurality of binary shift registers form a plurality of cross-connected binary LFCSRs with a plurality of reversible binary logic functions.
15. The descrambler of claim 10 , wherein the descrambler is self-synchronizing.
16. The descrambler of claim 10 , wherein the descrambler is part of a communication system.
17. The descrambler of claim 10 , wherein the descrambler is part of a storage system.
18. The descrambler of claim 10 , wherein the descrambler is part of a media player.
19. A method for descrambling with a descrambler a sequence of p scrambled n-state symbols with n equal to or greater than 2 and with p>1, each n-state symbol able to assume one of n states, into a sequence of p descrambled n-state symbols, comprising:
inputting an n-state symbol in the sequence of p scrambled n-state symbols on an input of an n-state shift register of an n-state Linear Forward Connected Shift Register (LFCSR) in Galois configuration and on an input of a multi-input n-state logic function in a tap of the n-state LFCSR;
receiving on a first input of a reversible n-state logic function an n-state symbol provided by an output of the n-state shift register;
receiving on a second input of the reversible n-state logic function the n-state symbol in the sequence of p scrambled n-state symbols; and
providing on an output of the reversible n-state logic function a descrambled n-state symbol in the sequence of p descrambled symbols.
20. The method of claim 19 , wherein an n-state symbol is received by an input through an n-state inverter.