Apparatus for efficient DCT calculations in a SIMD programmable processor

1. An apparatus for efficient and parallel implementation of digital signal processing algorithms in a single-instruction multiple-data (SIMD) processor, the apparatus comprising:

a vector register file for containing vector registers, wherein each vector register holds a plurality of vector elements of a predetermined size, said vector register file storing a first source vector, a second source vector, and a control vector;

a vector operation unit including a plurality of computing elements for performing a plurality of arithmetic/logical operations in parallel, each of said plurality of computing elements having a first input and a second input;

a first select logic for each vector element position coupled to respective said first input for selecting from a first list including but not limited to elements of said first source vector in accordance with said control vector;

a second select logic for each vector element position coupled to respective said second input for selecting from a second list including but not limited to elements of said second source vector in accordance with said control vector;

wherein said first list further includes elements of said second source vector and wherein said second list further includes elements of said first source vector; and

wherein each vector element stores a fixed-point or a floating-point number.

2. The apparatus according to claim 1 , wherein each input of vector operator can be pre-scaled by a predetermined amount before the operation in accordance with respective vector element of said control vector.

3. The apparatus according to claim 1 , wherein sign of each input of vector operator can be changed before the operation in accordance with respective vector element of said control vector.

4. The apparatus according to claim 1 , wherein an input of vector operator can be overridden to be zero accordance with respective vector element of said control vector.

5. The apparatus according to claim 1 , further including a vector accumulator coupled to output of said vector operation unit for accumulation of partial results in accordance with a vector instruction.

6. The apparatus according to claim 1 , further including a vector mask unit coupled to a write port of said vector register file for controlling storing of output to said vector register file on an element-by-element basis in accordance with a respective mask bit of said control vector.

7. The apparatus according to claim 5 , further including a vector clamping unit coupled to output of said vector accumulator for performing saturated arithmetic before storing result in a vector destination register of said vector register file.

8. The apparatus according to claim 1 , wherein three vector instruction formats are supported, in accordance with a format field of instruction word, in pairing elements of said first source vector and second source vector: respective element-to-element format as default, one-element broadcast format, and any-element-to-any-element format requiring a third source vector operand.

9. The apparatus according to claim 1 , further comprising means for performing inverse 4×4 DCT, whereby an integer 4×4 inverse DCT is performed in parallel according MPEG standard.

10. The apparatus according to claim 1 , further comprising means for performing one or more inverse 8-length DCT operations in parallel according to MPEG standard.

11. The apparatus according to claim 1 , further comprising means for calculating inverse 8×8 DCT in parallel according to MPEG standard.

12. The apparatus according to claim 1 , wherein number of vector elements for each vector register is an integer between 2 and 1025.

13. The apparatus according to claim 1 , wherein each vector element size is one of 16-bits, 32-bits, and 64-bits.