Wirebonded semiconductor package
In a method of manufacturing a semiconductor package including a wire binding process, a first end of the bonding wire is bonded to a first pad so as to form a first bond portion. A second end of the bonding wire is bonded to a second pad, wherein an interface surface between the bonding wire and the second pad has a first connecting area. The bonded second end of the bonding wire is scrubbed so as to form a second bond portion, wherein a new interface surface between the bonding wire and the second pad has a second connecting area larger than the first connecting area. A remainder of the bonding wire is separated from the second bond portion.
1. A semiconductor package, comprising:
a chip including a first pad located on an active surface of the chip;
a carrier including a second pad located on a surface of the carrier, wherein the chip is disposed on the carrier;
a bonding wire electrically connecting the chip to the carrier and comprising:
a first bond portion connected to the first pad; and
a second bond portion connected to the second pad, wherein the second bond portion includes a first concave portion, a second concave portion, and a protrusion between the first concave portion and the second concave portion, wherein the second bond portion includes a lower surface attached to the carrier, and at least a portion of the second concave portion is laterally displaced from the lower surface of the second bond portion; and
a molding compound encapsulating the chip and the bonding wire.
2. The semiconductor package as claimed in claim 1 , wherein:
the first concave portion extends from the protrusion to the carrier;
the second concave portion extends from the protrusion to a remaining portion of the bonding wire; and
the second concave portion is substantially linear in a direction extending along the protrusion.
3. The semiconductor package as claimed in claim 1 , wherein:
the bonding wire comprises a copper core and an anti-oxidative metallic layer covering the copper core;
the anti-oxidative metallic layer comprises palladium; and
the protrusion comprises both copper and palladium.
4. The semiconductor package as claimed in claim 1 , wherein the protrusion includes a scrubbed surface extending to a junction of the first concave portion and the second concave portion.
5. The semiconductor package as claimed in claim 1 , wherein:
the protrusion is laterally displaced from the lower surface of the second bond portion.
6. The semiconductor package as claimed in claim 1 , wherein:
the protrusion is directly above the lower surface of the second bond portion.
7. The semiconductor package as claimed in claim 1 , wherein:
the first concave portion extends from the protrusion to the carrier;
the second concave portion extends from the protrusion to a remaining portion of the bonding wire; and
the second concave portion has a width in the range from 1 μm to 10 μm, the width being along a direction substantially parallel to the carrier and extending lengthwise along the bonding wire.
8. A semiconductor package, comprising:
a substrate including a pad disposed on the substrate;
a wire bonded to the pad so as to form a bond portion connected to a remaining portion of the wire, wherein the bond portion includes a peak, a first curved surface extending from the peak to the substrate, and a second curved surface extending from the peak to the remaining portion of the wire, wherein the bond portion includes a lower surface attached to the pad, and at least a portion of the second curved surface is laterally displaced from the lower surface of the bond portion; and
a package body encapsulating the wire.
9. The semiconductor package of claim 8 , wherein:
the second curved surface is concave in a first direction from the peak to the remaining portion; and
the second curved surface is substantially linear in a second direction extending along the peak.
10. The semiconductor package of claim 8 , wherein:
the second curved surface is concave in a first direction from the peak to the remaining portion; and
the second curved surface is concave in a second direction extending along the peak.
11. The semiconductor package of claim 8 , wherein:
at least a portion of the first curved surface is directly above the lower surface of the bond portion.
12. The semiconductor package of claim 8 , wherein a majority of the second curved surface is laterally displaced from the lower surface of the bond portion.
13. The semiconductor package of claim 8 , wherein substantially all of the second curved surface is laterally displaced from the lower surface of the bond portion.
14. A semiconductor package, comprising:
a substrate including a pad disposed on the substrate;
a die disposed on the substrate;
a wire electrically connecting the die to the substrate, the wire being connected to the pad at a bond portion of the wire, wherein:
the bond portion includes a lower surface attached to the pad, a protrusion opposite the lower surface, a first indentation above the protrusion, and a second indentation below the protrusion;
at least a portion of the first indentation is laterally displaced from the lower surface of the bond portion; and
at least a portion of the second indentation is directly above the lower surface of the bond portion; and
a package body encapsulating the die and the wire.
15. The semiconductor package of claim 14 , wherein substantially all of the first indentation is laterally displaced from the lower surface of the bond portion.
16. The semiconductor package of claim 14 , wherein substantially all of the second indentation is directly above the lower surface of the bond portion.
17. The semiconductor package of claim 14 , wherein the protrusion is laterally displaced from the lower surface of the bond portion.
18. The semiconductor package of claim 14 , wherein the protrusion is directly above the lower surface of the bond portion.
19. The semiconductor package of claim 14 , wherein the first indentation has a width in the range from 1 μm to 10 μm, the width being along a direction substantially parallel to the substrate and extending lengthwise along the wire.
20. The semiconductor package of claim 14 , wherein:
the first indentation has a first width, the first width being along a direction substantially parallel to the substrate and extending lengthwise along the wire; and
the second indentation has a second width greater than the first width, the second width being along the direction parallel to the substrate and extending lengthwise along the wire.