IP Library Granted Patent US 8,370,712
Granted Patent B2
US 8,370,712 · App. 12/835,783 · Granted Feb 5, 2013

Memory management in a non-volatile solid state memory device

Inventors: Evangelos S Eleftheriou (Zurich, CH); Ilias Iliadis (Zurich, CH); Robert Haas (Zurich, CH); Xiaoyu Hu (Zurich, CH)
Assignee: International Business Machines Corporation
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Quick Facts
Patent No.
US 8,370,712
App. No.
12/835,783
Granted
Feb 5, 2013
Kind
B2
Abstract

A computer-implemented method of managing a memory of a non-volatile solid state memory device by balancing write/erase cycles among blocks to level block usage. The method includes: monitoring an occurrence of an error during a read operation in a memory unit of the device, wherein the error is correctable by error-correcting code; and programming the memory unit according to the monitored occurrence of the error; wherein the step of monitoring the occurrence of an error is carried out for at least one block; and wherein said step of programming comprises wear-leveling the monitored block according the error monitored for the monitored block. A computer system and a computer program-product is also provided. The non-volatile solid state memory device includes: a memory unit having data stored therein; and a controller with a logic for programming the memory unit according to a monitored occurrence of an error during a read operation. The method includes: monitoring an occurrence of an error during a read operation in a memory unit of the device; and programming the memory unit according to the monitored occurrence of the error.

Claims (16)

1. A computer-implemented method of managing a memory of a non-volatile solid state memory device by balancing write/erase cycles among blocks to level block usage, said method comprising:

monitoring an occurrence of an error during a read operation in a memory unit of said device, wherein (i) said memory unit is subdivided into dice, and each said die comprises at least one block, (ii) said error is correctable by error-correcting code, and (iii) said monitoring is carried out for said at least one block;

programming said memory unit according to said monitored occurrence of said error, wherein said programming comprises wear-leveling said monitored block according to said error monitored for said monitored block; and

if said at least one block is writable, setting apart said writable block of said memory unit, and wherein wear-leveling is implemented for a block that is distinct from said writable block that has been set apart.

2. The method according to claim 1 , wherein said step of monitoring the occurrence of an error comprises monitoring the rate of errors.

3. The method according to claim 1 , wherein said step of monitoring the occurrence of an error that is carried out for each said block is also carried out for each of said die, and preferably by maintaining a per-block counter of said occurrence of said error.

4. The method according to claim 1 , wherein said step of monitoring the occurrence of an error comprises monitoring an error in a window of maximum of consecutive read operations.

5. The method according to claim 1 , further comprising:

maintaining a per-block counter of write-erase data, and

wherein said step of programming said memory is carried out according to both said error monitored and said write-erase data maintained.

6. The method according to claim 1 , wherein said step of setting apart a writable block is performed independent of the number of said errors monitored or the number of write-erase operations performed in each said block of said memory unit.

7. The method according to claim 1 , wherein said step of setting apart a writable block is decided and/or refined based on the number of said errors monitored or said write-erase data maintained.

8. The method according to claim 2 , further comprising:

releasing and using said writable block that has been set apart, wherein said step of releasing and using said writable block that has been set apart is performed if said monitored occurrence of an error or rate of errors exceeds a threshold indicative of a depletion of writable memory space in said memory unit.

9. The method according to claim 8 , further comprising initiating a migration of data towards another memory device, wherein said step of initiating a migration of data towards another memory device is performed if said monitored occurrence of said error or said rate of errors exceeds a threshold indicative of a depletion of writable memory space in said memory unit.

10. An article of manufacture tangibly embodying non-transitory computer readable instructions which when implemented, causes a computerized system to carry out the steps of the method of managing a memory of a non-volatile solid state memory device according to claim 1 .

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2014
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: SK HYNIX INC.
Reel/Frame 033417/0880 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2010
From: ELEFTHERIOU, EVANGELOS; ILIADIS, ILIAS; HAAS, ROBERT; HU, XIAOYU
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 024680/0167 →
Priority Claims (1)
EP 09166231 · Jul 23, 2009 · regional
Continuity (1)
Related Publication 20110022931A1 · Jan 27, 2011