On-chip inductor structure and method for manufacturing the same
The present invention relates to a an on-chip inductor structure and a method for manufacturing the same. The an on-chip inductor structure according to the present invention comprises a substrate, a porous layer, a plurality of conductors, and an inductor. The porous layer is disposed on the substrate and has a plurality of voids; each of the plurality of conductors is disposed in the plurality of voids, respectively; and the inductor is disposed on the porous layer. Because the plurality of conductors is used as the core of the inductor, the inductance is increased effectively and the area of the an on-chip inductor is reduced. Besides the manufacturing method according to the present invention is simple and compatible with the current CMOS process, the manufacturing cost can be lowered.
1. An on-chip inductor structure, comprising:
a substrate;
a porous layer, disposed on said substrate, and having a plurality of voids;
a plurality of conductors, disposed in said plurality of voids, said conductors are pillar shaped, the depth-to-width ratio of said conductors is greater than 3:1; and
an inductor, disposed on said porous layer.
2. The on-chip inductor structure of claim 1 , and further comprising an insulation layer, disposed on said substrate, and between said substrate and said porous layer.
3. The on-chip inductor structure of claim 1 , and further comprising an insulation layer, disposed on said porous layer, and between said porous layer and said inductor.
4. The on-chip inductor structure of claim 1 , wherein said inductor includes a plurality of coils.
5. The on-chip inductor structure of claim 1 , wherein said porous layer is a nanometer porous layer.
6. The on-chip inductor structure of claim 1 , wherein the material of said plurality of conductors is a ferromagnetic material.
7. The on-chip inductor structure of claim 6 , wherein the material of the ferromagnetic material includes nickel.
8. The on- chip inductor structure of claim 1 , wherein said conductors are pillar shaped.
9. The on-chip inductor structure of claim 1 , wherein said porous layer is a nonconductor.
10. The on-chip inductor structure of claim 1 , wherein said porous layer is an aluminum oxide layer.