IP Library Granted Patent US 8,378,496
Granted Patent B2
US 8,378,496 · App. 12/670,303 · Granted Feb 19, 2013

Semiconductor substrate with interlayer connection and method for production of a semiconductor substrate with interlayer connection

Inventors: Franz Schrank (Graz, AT); Martin Schrems (Eggersdorf, AT); Jochen Kraft (Oberaich, AT)
Assignee: austriamicrosystems AG
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Quick Facts
Patent No.
US 8,378,496
App. No.
12/670,303
Granted
Feb 19, 2013
Kind
B2
Abstract

The interlayer connection of the substrate is formed by a contact-hole filling ( 4 ) of a semiconductor layer ( 11 ) and metallization ( 17 ) of a recess ( 16 ) in a reverse-side semiconductor layer ( 13 ), wherein the semiconductor layers are separated from each other by a buried insulation layer ( 12 ), at whose layer position the contact-hole filling or the metallization ends.

Claims (65)

1. A semiconductor substrate with interlayer connection, comprising:

layers of semiconductor material and an insulation layer arranged between the layers of semiconductor material, the insulation layer being a multiple layer;

at least one contact-hole filling arranged in a layer of the layers of semiconductor material, the contact-hole filling penetrating said layer,

a recess arranged in and penetrating a layer of semiconductor material opposite to the contact-hole filling, and being provided with a metallization; and

an electrically conductive contact between the contact-hole filling and the metallization, the electrically conductive contact being arranged in the insulation layer.

2. The semiconductor substrate according to claim 1 , wherein the insulation layer comprises at least one of (i) a nitride layer and (ii) at least one oxide layer.

3. The semiconductor substrate according to claim 1 , wherein the insulation layer is an oxide-nitride-oxide layer sequence.

4. A method of producing a semiconductor substrate with interlayer connection, comprising:

a substrate of semiconductor material being provided with an insulation layer embedded in the semiconductor material;

producing at least one opening in the substrate, using a mask, the insulation layer being exposed in the opening;

forming a dielectric layer covering the semiconductor material in the opening;

introducing an electrically conductive material into the opening, forming a contact-hole filling;

producing a recess in the substrate opposite to the contact-hole filling, the insulation layer being exposed in the recess;

forming a further dielectric layer covering the semiconductor material in the recess;

exposing the contact-hole filling from the recess;

applying a metallization in the recess, the metallization electrically contacting the contact-hole filling; and

forming a contact area, the contact area being electrically connected to the contact-hole filling.

5. The method according to claim 4 , further comprising:

with the substrate being an SOI substrate having a body silicon layer and a bulk silicon layer, arranging the insulation layer between the body silicon layer and the bulk silicon layer;

producing the opening in the body silicon layer; and

producing at least one electronic component in the body silicon layer.

6. The method according to claim 4 , further comprising:

forming the substrate of a semiconductor body;

providing the semiconductor body with a laterally confined insulation layer on a surface of the semiconductor body;

applying further semiconductor material, the insulation layer being embedded in the semiconductor material; and

planarizing the semiconductor material.

7. The method according to claim 4 , further comprising:

thinning the insulation layer in the opening to a residual layer portion before the electrically conductive material is introduced into the opening;

depositing the electrically conductive material on the residual layer portion of the insulation layer;

etching such that the residual layer portion of the insulation layer is an etching stop layer during the production of the recess; and

removing the residual layer portion of the insulation layer from the contact-hole filling before the application of the metallization.

8. A method for producing a semiconductor substrate with interlayer connection, comprising:

providing a substrate of semiconductor material with an opening with inner surfaces, using a mask;

forming a dielectric layer on the inner surfaces of the opening;

introducing an electrically conductive material into the opening, forming a contact-hole filling;

thinning the substrate from a reverse side opposite to the contact-hole filling until a reverse-side surface of the contact-hole filling is exposed;

forming a bonding layer on the reverse side;

fastening a wafer to the bonding layer;

producing a recess in the wafer;

forming a further dielectric layer covering the semiconductor material in the recess;

exposing the contact-hole filling from the reverse side;

applying a metallization in the recess, the metallization electrically contacting the contact-hole filling; and

forming a contact area, the contact area being electrically connected to the contact-hole filling.

9. The method according to claim 8 , wherein the contact-hole filling is formed from electrically conductive doped polysilicon.

10. The method according to claim 9 , further comprising:

producing CMOS components after the production of the contact-hole filling;

forming a wiring by metallization layers and intermetal dielectric, the contact-hole filling being electrically connected to the contact area; and

subsequently producing the recess on the side of the insulation layer opposite to the contact-hole filling.

11. The method according to claim 8 , wherein the contact-hole filling is formed from metal.

12. The method according to claim 11 , comprising:

producing CMOS components before the production of the contact-hole filling;

forming a wiring by metallization layers and intermetal dielectric after the production of the contact-hole filling, the contact-hole filling being electrically connected to the contact area; and

subsequently producing the recess on the side of the insulation layer opposite to the contact-hole filling.

13. The method according to claim 8 , further comprising:

providing a further contact area on the reverse side and being connected to the metallization; and

applying a solder ball covering the recess on the further contact area.

14. The method according to claim 4 , wherein the contact-hole filling is formed from electrically conductive doped polysilicon.

15. The method according to claim 4 , wherein the contact-hole filling is formed from metal.

16. The method according to claim 15 , comprising:

producing CMOS components before the production of the contact-hole filling;

forming a wiring by metallization layers and intermetal dielectric after the production of the contact-hole filling, the contact-hole filling being electrically connected to the contact area; and

subsequently producing the recess on the side of the insulation layer opposite to the contact-hole filling.

17. The method according to claim 4 , further comprising:

providing a further contact area on the reverse side and being connected to the metallization; and

applying a solder ball covering the recess on the further contact area.

Assignments (3)
CHANGE OF NAME Recorded Dec 18, 2025
From: AMS AG
To: AMS-OSRAM AG
Reel/Frame 073886/0373 →
CHANGE OF NAME Recorded Dec 18, 2025
From: AUSTRIAMICROSYSTEMS AG
To: AMS AG
Reel/Frame 073886/0430 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 17, 2010
From: SCHRANK, FRANZ; SCHREMS, MARTIN; KRAFT, JOCHEN
To: AUSTRIAMICROSYSTEMS AG
Reel/Frame 024554/0918 →
Priority Claims (1)
DE 10 2007 034 306 · Jul 24, 2007 · national
Continuity (1)
Related Publication 20100314762A1 · Dec 16, 2010