Method for circuit layout and rapid thermal annealing method for semiconductor apparatus
The present invention provides a design method for circuit layout and a rapid thermal annealing method for a semiconductor apparatus. The design method includes: establishing a ternary relationship among a device electric parameter, an annealing temperature and a distributing density of STI patterns, and establishing a binary relationship between the device electric parameter and a gate pattern length; obtaining a difference between distributing densities of STI patterns in a particular region and in a target region; obtaining an electric parameter difference corresponding to the difference between the distributing densities of STI patterns according to the ternary relationship; obtaining a gate pattern length difference corresponding to the electric parameter difference according to the binary relationship; and adjusting a gate pattern length in the particular region according to the gate pattern length difference. As compared with a traditional design method, the design method for circuit layout provided by the invention does not need adding dummy structure patterns, thereby avoiding negative influence to normal electric performance of the semiconductor apparatus by adding dummy structures.
1. A method for manufacturing a semiconductor device, comprising:
establishing a ternary relationship among a device electric parameter, an annealing temperature and a distributing density of Shallow Trench Isolation (STI) patterns, and establishing a binary relationship between the device electric parameter and a gate pattern length;
obtaining a difference between distributing densities of STI patterns in a particular region and in a target region;
obtaining an electric parameter difference corresponding to the difference between the distributing densities of STI patterns according to the ternary relationship;
obtaining a gate pattern length difference corresponding to the electric parameter difference according to the binary relationship;
adjusting a gate pattern length in the particular region according to the gate pattern length difference; and
making a photo mask of gate patterns with the adjusted gate pattern length.
2. The method according to claim 1 , wherein the obtaining of a difference between distributing densities of STI patterns in a particular region and in a target region comprises:
obtaining a distributing density of STI patterns in the target region, D 0 ;
obtaining a distributing density of STI patterns in the particular region, D x ; and
calculating a difference between D x and D 0 .
3. The method according to claim 2 , wherein the obtaining of a distributing density of STI patterns in the target region, D 0 , comprises:
determining a target electric parameter according to a design requirement of a semiconductor apparatus; and
obtaining a distributing density of STI patterns corresponding to the target electric parameter, which is the distributing density of STI patterns in the target region, D 0 , according to the ternary relationship among the device electric parameter, the annealing temperature and the distributing density of STI patterns.
4. The method according to claim 2 , wherein the obtaining of a distributing density of STI patterns in the particular region, D x , comprises:
dividing the circuit layout into a plurality of repeating regions;
detecting a distributing density of active areas A x and a distributing density of gate patterns P x in each of the regions respectively;
calculating a distributing density of STI patterns in each of the regions according to the equation: D x =(1−A x )×(1−P x ); and
judging whether the distributing density of STI patterns in each of the regions equals to the distributing density of STI patterns in the target region, and if not, determining the region as the particular region.
5. The method according to claim 1 , wherein the particular region is a dummy structure-sensitive region.
6. The method according to claim 1 , wherein the electric parameter comprises a saturation current or a threshold voltage.
7. The method according to claim 1 , wherein the ternary relationship among the device electric parameter, the annealing temperature, and the distributing density of STI is a linear relationship.
8. The method according to claim 1 , wherein the binary relationship between the device electric parameter and the gate pattern length is a linear relationship.
9. A method for manufacturing a semiconductor apparatus, comprising:
establishing a ternary relationship among a device electric parameter, an annealing temperature and a distributing density of Shallow Trench Isolation (STI) patterns, and establishing a binary relationship between the device electric parameter and a gate pattern length;
obtaining a difference between distributing densities of STI patterns in a particular region and in a target region;
obtaining an electric parameter difference corresponding to the difference between the distributing densities of STI patterns according to the ternary relationship;
obtaining a gate pattern length difference corresponding to the electric parameter difference according to the binary relationship; and
adjusting a gate pattern length in the particular region according to the gate pattern length difference;
making a gate in the particular region of the semiconductor apparatus by using an adjusted gate pattern; and
obtaining a target annealing temperature corresponding to the distributing density of STI patterns in the particular region according to the ternary relationship, and performing an annealing process on the semiconductor apparatus with the annealing temperature, to achieve a target electric parameter.
10. The method according to claim 9 , wherein the ternary relationship among the device electric parameter, the annealing temperature and the distributing density of STI patterns is a linear relationship.
11. The method according to claim 9 , wherein the obtaining of a difference between distributing densities of STI patterns in a particular region and in a target region comprises:
obtaining a distributing density of STI patterns in the target region, D 0 ;
obtaining a distributing density of STI patterns in the particular region, D x ; and
calculating a difference between D x and D 0 .
12. The method according to claim 11 , wherein the obtaining of a distributing density of STI patterns in the target region, D 0 , comprises:
determining a target electric parameter according to a design requirement of a semiconductor apparatus; and
obtaining a distributing density of STI patterns corresponding to the target electric parameter, which is the distributing density of STI patterns in the target region, D 0 , according to the ternary relationship among the device electric parameter, the annealing temperature and the distributing density of STI patterns.
13. The method according to claim 11 , wherein the obtaining of a distributing density of STI patterns in the particular region, D x , comprises:
dividing the circuit layout into a plurality of repeating regions;
detecting a distributing density of active areas A x and a distributing density of gate patterns P x in each of the regions respectively;
calculating a distributing density of STI patterns in each of the regions according to the equation: D x =(1−A x )×(1−P x );and
judging whether the distributing density of STI patterns in each of the regions equals to the distributing density of STI patterns in the target region, and if not, determining the region as the particular region.
14. The method according to claim 9 , wherein the particular region is a dummy structure-sensitive region.
15. The method according to claim 9 , wherein the electric parameter comprises a saturation current or a threshold voltage.
16. The method according to claim 9 , wherein the binary relationship between the device electric parameter and the gate pattern length is a linear relationship.