Voltage boosting in MRAM current drivers

1. A current driving mechanism for a magnetic memory device, comprising:

a current driver circuit: and

a current decoding block coupled to the current driver circuit, wherein the current decoding block comprises

a transistor (M 18 ) to control driver currents from the current driver circuit, and

a transistor (M 22 ) and an inverter (I 4 ), wherein the transistor (M 22 ) isolates a negative voltage from the inverter (I 4 ), and wherein the transistor (M 22 ) facilitates maintenance of the negative voltage at a gate of the transistor (M 18 ), thereby allowing a reduced form factor for the transistor (M 18 ) by virtue of maintaining the gate thereof at the negative voltage.

2. The current driving mechanism of claim 1 , wherein a voltage high signal passes freely from the inverter (I 4 ) through the transistor (M 22 ) to a node ( 43 ) of the current decoding block when a row/column is unselected.

3. The current driving mechanism of claim 2 , wherein a logic high on the node ( 43 ) turns off the transistor (M 18 ) to prevent current passing from the current driver circuit to rows/columns.

4. The current driving mechanism of claim 3 , wherein the current decoding block comprises an arrangement of components to hold the node ( 43 ) at a voltage below zero to drive the gate of the transistor (M 18 ) to below zero.

5. The current driving mechanism of claim 1 , wherein the gate of the transistor (M 18 ) is kept at −3V.

6. A magnetic random access memory (MRAM) chip comprising:

an array of memory cells; and

a current driving mechanism coupled to the array of memory cells, the current driving mechanism comprising

a current driver circuit; and

a current decoding block coupled to the current driver circuit, wherein the current decoding block comprises

a transistor (M 18 ) to control driver currents from the current driver circuit, and

a transistor (M 22 ) and an inverter (I 4 ), wherein the transistor (M 22 ) isolates a negative voltage from the inverter (I 4 ), and wherein the transistor facilitates maintenance of the negative voltage at a gate of the transistor (M 18 ), thereby allowing a reduced form factor for the transistor (M 18 ) by virtue of maintaining the gate thereof at the negative voltage.

7. The MRAM chip of claim 6 , wherein a voltage high signal passes freely from the inverter (I 4 ) through the transistor (M 22 ) to a node ( 43 ) of the current decoding block when a row/column is unselected.

8. The MRAM chip of claim 7 , wherein a logic high on the node ( 43 ) turns off the transistor (M 18 ) to prevent current passing from the current driver circuit to rows/columns.

9. The MRAM chip of claim 8 , wherein the current decoding block comprises an arrangement of components to hold the node ( 43 ) at a voltage below zero to drive the gate of the transistor (M 18 ) to below zero.

10. The MRAM chip of claim 6 , wherein the gate of the transistor (M 18 ) is kept at ˜3V.

11. A magnetic random access memory (MRAM) device comprising:

a MRAM chip having an array of memory cells and a current driving mechanism coupled to the array of memory cells, the current driving mechanism comprising

a current driver circuit; and

a current decoding block coupled to the current driver circuit, wherein the current decoding block comprises

a transistor (M 18 ) to control driver currents from the current driver circuit, and

a transistor (M 22 ) and an inverter (I 4 ), wherein the transistor (M 22 ) isolates a negative voltage from the inverter (I 4 ), and wherein the transistor (M 22 ) facilitates maintenance of the negative voltage at a gate of the transistor (M 18 ), thereby allowing a reduced form factor for the transistor (M 18 ) by virtue of maintaining the gate thereof at the negative voltage.

12. The MRAM device of claim 11 , wherein a voltage high signal passes freely from the inverter ( 14 ) through the transistor (M 22 ) to a node ( 43 ) of the current decoding block when a row/column is unselected.

13. The MRAM device of claim 12 , wherein a logic high on the node ( 43 ) turns off the transistor (M 18 ) to prevent current passing from the current driver circuit to rows/columns.

14. The MRAM device of claim 13 , wherein the current decoding block comprises an arrangement of components to hold the node ( 43 ) at a voltage below zero to drive the gate of the transistor (M 18 ) to below zero.

15. A current driving mechanism for a magnetic memory device, comprising:

a current driver circuit; and

a current decoding block coupled to the current driver circuit, wherein the current decoding block comprises

a transistor (M 30 ) to control driver currents from the current driver circuit; and

a high voltage switch coupled to the transistor (M 30 ) to boost a voltage of a selected gate of the transistor (M 30 ) to a higher level, thereby allowing a reduced form factor for the transistor (M 30 ) by virtue of said boosting; and

a charge pump circuit to disposed between the current driver circuit and the current decoding block to drive the high voltage switch.

16. The current driving mechanism of claim 15 , wherein an associated line for selected rows and columns of the current decoding block is held at 0 volts.

17. The current driving mechanism of claim 15 , where the gate of the transistor (M 30 ) is held at 5V.

18. The current driving arrangement of claim 1 , wherein the arrangement of components includes a combination of (M 23 ) as a switch, (M 24 ) and (M 25 ) connected as diodes, and (C 1 ) and (C 2 ) connected as capacitors.

19. The MRAM chip of claim 6 , wherein the arrangement of components includes a combination of (M 23 ) as a switch, (M 24 ) and (M 25 ) connected as diodes, (C 1 ) and (C 2 ) connected as capacitors.

20. The MRAM device of claim 11 , wherein the arrangement of components includes a combination of (M 23 ) as a switch, (M 24 ) and (M 25 ) connected as diodes, (C 1 ) and (C 2 ) connected as capacitors.