IP Library Granted Patent US 8,401,064
Granted Patent B1
US 8,401,064 · App. 12/973,819 · Granted Mar 19, 2013

Systems, circuits and methods for adapting parameters of components in a receiver

Inventors: Andrew Lin (Menlo Park, CA); Faramarz Bahmani (San Jose, CA)
Assignee: NetLogic Microsystems, Inc.
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Quick Facts
Patent No.
US 8,401,064
App. No.
12/973,819
Granted
Mar 19, 2013
Kind
B1
Abstract

A receiver is optimized by adapting parameters of components within the receiver. Various component parameters are adapted by using either a least means squared algorithm or a steepest descent algorithm. The taps of a decision feedback equalizer can be adapted by using either a least means squared algorithm or a steepest descent algorithm. The gain value of a linear equalizer and the input of a digital to analog converter coupled to the linear equalizer are also adapted through the least means squared algorithm or a steepest descent algorithm. A variable gain amplifier is also capable of being adapted through the use of the least means squared algorithm. Clock offsets are also configured by use of a steepest descent algorithm.

Claims (31)

1. A method for adapting parameters of components in a receiver, comprising:

adapting a plurality of taps of a decision feedback equalizer by using a least means squared algorithm;

configuring a parameter of a linear equalizer by using a steepest descent algorithm to select a value of the parameter that minimizes a signal error rate;

varying a gain of a variable gain amplifier by using the least means squared algorithm; and

adjusting a clock offset by using the steepest descent algorithm to select a value of the clock offset that minimizes the signal error rate, wherein the adjusting of the clock offset changes a sampling point of a data slicer and an error slicer.

2. The method of claim 1 , wherein configuring a parameter of a linear equalizer comprises configuring an input of a digital to analog converter coupled to the linear equalizer, the output of the digital to analog converter for injecting into the linear equalizer.

3. The method of claim 1 , wherein configuring a parameter of a linear equalizer comprises configuring a gain value of the linear equalizer.

4. The method of claim 1 , wherein using the steepest descent algorithm comprises a gradient function to determine a direction which decreases the signal error rate most rapidly.

5. The method of claim 1 , wherein the least means squared algorithm and the steepest descent algorithm are performed by a microcontroller.

6. The method of claim 1 , wherein the signal error rate is measured by counting a number of margin hits, wherein a margin hit is counted by sampling an output signal eye from a summer.

7. The method of claim 1 , further comprising calibrating a slicer within the decision feedback equalizer when the receiver is reset, wherein the calibration comprises the injection of a current from a second digital to analog converter into the slicer.

8. A system for adapting parameters of components in a receiver, comprising:

a decision feedback equalizer comprising a plurality of taps for adaptation by using a least means squared algorithm;

a linear equalizer comprising a parameter for configuration by using a steepest descent algorithm to select a value of the parameter that minimizes a signal error rate;

a variable gain amplifier comprising a gain value for varying by using the least means squared algorithm; and

a clock offset module for adjusting a clock offset value by using the steepest descent algorithm to select a value for the clock offset that minimizes the signal error rate, wherein the adjusting of the clock offset value changes a sampling point of a data slicer and an error slicer.

9. The system of claim 8 , wherein the parameter of the linear equalizer comprises an input of a digital to analog converter coupled to the linear equalizer, the output of the digital to analog converter injected into the linear equalizer.

10. The system of claim 8 , wherein the parameter of the linear equalizer comprises a gain value of the linear equalizer.

11. The system of claim 8 , wherein the steepest descent algorithm comprises a gradient function to determine a direction which decreases the signal error rate most rapidly.

12. The system of claim 8 , wherein the least means squared algorithm and the steepest descent algorithm are performed by a microcontroller.

13. The system of claim 8 , wherein the signal error rate is measured by counting a number of margin hits, wherein a margin hit is counted by sampling an output signal eye from a summer.

14. The system of claim 8 , further comprising calibrating a slicer within the decision feedback equalizer when the receiver is reset, wherein the calibration comprises the injection of a current from a second digital to analog converter into the slicer.

15. A method for adapting parameters of components in a receiver, comprising:

adapting a tap of a decision feedback equalizer by using a steepest descent algorithm to select a value for the tap that minimizes a signal error rate;

configuring a parameter of a linear equalizer by using a steepest descent algorithm to minimize the signal error rate;

varying a gain of a variable gain amplifier by using a least means squared algorithm; and

adjusting a clock offset by using the steepest descent algorithm to minimize the signal error rate, wherein the adjusting of the clock offset changes a sampling point of a data slicer and an error slicer.

16. The method of claim 15 , wherein configuring a parameter of a linear equalizer comprises configuring an input of a digital to analog converter coupled to the linear equalizer, the output of the digital to analog converter for injecting into the linear equalizer.

17. The method of claim 15 , wherein using the steepest descent algorithm comprises using a gradient function to determine a direction which decreases the signal error rate most rapidly.

18. The method of claim 15 , wherein the least means squared algorithm and the steepest descent algorithm are performed by a microcontroller.

19. The method of claim 15 , wherein the signal error rate is measured by counting a number of margin hits, wherein a margin hit is counted by sampling an output signal eye from a summer.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: NETLOGIC I LLC
To: BROADCOM CORPORATION
Reel/Frame 035443/0763 →
CHANGE OF NAME Recorded Apr 16, 2015
From: NETLOGIC MICROSYSTEMS, INC.
To: NETLOGIC I LLC
Reel/Frame 035443/0824 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2012
From: BAHMANI, FARAMARZ
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 027711/0511 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2010
From: LIN, ANDREW
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 025538/0852 →