Test device and a semiconductor integrated circuit device
A test device includes a semiconductor substrate having a first test region and a second test region defined thereon, wherein a layout of the first test region includes first active regions separated from each other by isolation regions in the semiconductor substrate, second active regions formed between the first active regions, first gate lines formed on the semiconductor substrate, wherein each of the first gate lines has a first end adjacent to one of the first active regions and a second end adjacent to an end of one of the second active regions, respectively, first shared contacts each formed over a respective one of the second ends of the first gate lines and an upper part of one of the first active regions, and first nodes formed on the first shared contacts to be electrically connected to the first shared contacts, respectively.
1. A test device, comprising:
a semiconductor substrate having a first test region and a second test region defined thereon,
wherein a layout of the first test region includes a pair of first active regions separated from each other by isolation regions in the semiconductor substrate, a pair of second active regions formed between the first active regions, a pair of first gate lines formed on the semiconductor substrate, wherein each of the first gate lines has a first end adjacent to one of the first active regions and a second end adjacent to an end of one of the second active regions, respectively, a pair of first shared contacts each formed over a respective one of the second ends of the first gate lines and an upper part of one of the second active regions, and a pair of first nodes formed on the first shared contacts to be electrically connected to the first shared contacts, respectively,
wherein a layout of the second test region includes a pair of third active regions, a pair of fourth active regions, a pair of second shared contacts, and a pair of second nodes, wherein the pair of third active regions is surrounded by the isolation regions in the semiconductor substrate to correspond to the first active regions, the pair of fourth active regions is formed between the third active regions to correspond to the second active regions, each of the pair of second shared contacts is formed on part of one of the fourth active regions, part of one of the isolation regions and not a gate line, respectively, to correspond to the first shared contacts, and the pair of second nodes is formed to correspond to the first nodes to be electrically connected to the second shared contacts, respectively,
wherein the layout of the first test region further comprises a first current detection part that determines whether current flows between the pair of first nodes, and
wherein the layout of the second test region further comprises a second current detection part that determines whether current flows between the pair of second nodes.
2. The test device of claim 1 , wherein leakage current caused by at least one of the first gate lines is measured by determining whether current flows between the pair of first nodes and between the pair of second nodes.
3. The test device of claim 1 , further comprising a static memory cell region defined on the semiconductor substrate, wherein the static memory cell region has the same layout as the first test region.