Semiconductor device and method for manufacturing the same

1. A method of forming a dual contact plug, comprising steps of:

forming a source/drain region and a replacement gate structure on a semiconductor substrate, the replacement gate structure including a replacement gate;

depositing a first inter-layer dielectric layer;

planarizing the first inter-layer dielectric layer to expose the replacement gate in the replacement gate structure;

completely removing the entire replacement gate to form an opening and depositing metal gate material into the opening to form a metal gate by means of replacement gate process;

etching to form a first source/drain contact opening in the first inter-layer dielectric layer by means of lithography so that the source/drain region formed on the semiconductor substrate is exposed at the bottom of the first source/drain contact opening;

sequentially depositing a liner and filling conductive metal in the first source/drain contact opening to form a first source/drain contact plug;

depositing a second inter-layer dielectric layer on the first inter-layer dielectric layer with the first source/drain contact plug formed therein;

etching to form a second source/drain contact opening and a gate contact opening in the second inter-layer dielectric layer by means of lithography so that the first source/drain contact plug is exposed at the bottom of the second source/drain contact opening and the metal gate is exposed at the bottom of the gate contact opening; and

sequentially depositing a liner and filling conductive metal in the second source/drain contact opening and the gate contact opening to form a second source/drain contact plug and a gate contact plug.

2. The method according to claim 1 , wherein

the width of the first source/drain contact plug is 15-100 nm,

the width of the second source/drain contact plug is 20-150 nm, and

the width of the gate contact plug is 20-150 nm.

3. The method according to claim 1 , wherein

the conductive metal in the second source/drain contact plug and the gate contact plug has a resistivity smaller than that of the conductive metal in the first source/drain contact plug.

4. The method according to claim 1 , further comprising a step of:

forming a barrier liner entirely on the semiconductor substrate with the source/drain region and the replacement gate structure formed thereon, before depositing the first inter-layer dielectric layer.

5. The method according to claim 4 , wherein

the barrier liner includes Si 3 N 4 and has a thickness of 10-50 nm.

6. The method according to claim 1 , further comprising a step of: forming a barrier layer entirely on the first inter-layer dielectric layer with the first source/drain contact plug formed therein, before depositing the second inter-layer dielectric layer.

7. The method according to claim 6 , wherein

the barrier layer includes Si 3 N 4 and has a thickness of 10-50 nm.

8. The method according to claim 1 , wherein

the liner in the first source/drain contact opening and/or the liner in the second source/drain contact opening and the gate contact opening includes at least one selected from TiN, TaN, Ta and Ti, and

the conductive metal in the first source/drain contact opening and/or the conductive metal in the second source/drain contact opening and the gate contact opening includes at least one selected from Ti, Al, TiAl, Cu and W.

9. The method according to claim 1 , wherein

the replacement gate is a polysilicon gate.

10. The method according to claim 1 , wherein

the thickness of the first inter-layer dielectric layer is 15-50 nm, and

the thickness of the second inter-layer dielectric layer is 25-90 nm.