IP Library › Granted Patent US 8,413,024
Granted Patent B2
US 8,413,024 · App. 13/484,787 · Granted Apr 2, 2013

Performing a cyclic redundancy checksum operation responsive to a user-level instruction

Inventors: Steven R. King (Portland, OR); Frank Berry (North Plains, OR); Michael E. Kounavis (Hillsboro, OR)
Assignee: Intel Corporation
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Quick Facts
Patent No.
US 8,413,024
App. No.
13/484,787
Granted
Apr 2, 2013
Kind
B2
Abstract

In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Claims (2)

1. A processor comprising:

logic to perform a user-level instruction, wherein the logic is to perform at least one exclusive-OR operation on data of one of a variable number of data sizes responsive to the user-level instruction.

Continuity (3)
Continuation 13097462 · Apr 29, 2011
Continuation 11316772 · Dec 23, 2005
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