IP Library Granted Patent US 8,415,089
Granted Patent B1
US 8,415,089 · App. 12/723,798 · Granted Apr 9, 2013

Single-mask double-patterning lithography

Inventors: Puneet Gupta (Los Angeles, CA); Rani S. Ghaida (Los Angeles, CA)
Assignee: The Regents of the University of California
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Quick Facts
Patent No.
US 8,415,089
App. No.
12/723,798
Granted
Apr 9, 2013
Kind
B1
Abstract

A method of printing a final layout on a wafer comprises printing a first pattern from a first mask located at a first position onto the wafer, shifting the first mask by a predetermined distance to a second position, printing the first pattern from the first mask located at the second position onto the wafer, and applying a trim mask to the wafer.

Claims (13)

1. A method of printing a layout on a wafer comprising:

printing a first pattern from a first mask located at a first position onto the wafer;

shifting the first mask by a predetermined distance to a second position; and

printing the first pattern from the first mask located at the second position onto the wafer such that the first pattern is superimposed upon itself after shifting the first mask by the predetermined distance to thereby provide a superset of a desired final layout.

2. The method of claim 1 wherein printing the first pattern located at the first position and printing the first pattern located at the second position comprises a lithographic process.

3. The method of claim 2 wherein the lithographic process is selected from a group consisting of a positive dual-line litho-etch-litho-etch (LELE) process, a negative dual-trench LELE process, a positive dual-line litho-litho-etch (LLE) process, and a negative dual-trench LLE process.

4. The method of claim 1 wherein the first mask is a photomask.

5. The method of claim 1 wherein the predetermined distance is equal to a minimum features pitch of the desired final layout.

6. The method of claim 5 wherein the minimum features pitch is a minimum gate pitch.

7. The method of claim 1 wherein the first pattern is comprised of one or more vertical lines and no more than two horizontal lines per standard-cell layout.

8. The method of claim 7 wherein each of the no more than two horizontal lines is restricted to a position selected from a group consisting of a top of the first pattern and a bottom of the first pattern.

9. The method of claim 7 further comprising decomposing the desired final layout into the first pattern.

10. The method of claim 1 further comprising applying a trim mask to the wafer to provide the desired final layout.

Assignments (2)
CONFIRMATORY LICENSE Recorded May 14, 2010
From: UNIVERSITY OF CALIFORNIA LOS ANGELES
To: NATIONAL SCIENCE FOUNDATION
Reel/Frame 024384/0749 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2010
From: GUPTA, PUNEET; GHAIDA, RANI S.
To: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
Reel/Frame 024078/0900 →