IP Library Granted Patent US 8,416,230
Granted Patent B2
US 8,416,230 · App. 12/623,165 · Granted Apr 9, 2013

Embedded display power management

Inventor: Dimitry Goder (San Jose, CA)
Assignee: Synaptics Incorporated
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Quick Facts
Patent No.
US 8,416,230
App. No.
12/623,165
Granted
Apr 9, 2013
Kind
B2
Abstract

An integrated circuit is disclosed that includes a display management circuitry configured to control the operation of a display panel in combination with a power management circuitry configured to control the power consumption of a panel backlight.

Claims (22)

1. An integrated circuit comprising:

display management circuitry configured to control the operation of a display panel; and

power management circuitry configured to control the power consumption of a panel backlight from an overvoltage and a feedback voltage measured from the panel backlight, the feedback voltage and the overvoltage being determined by voltages on opposite sides of the panel backlight, and wherein the panel backlight is a light-emitting diode (“LED”) backlight, wherein:

the feedback voltage and a first threshold voltage is compared in a comparator to generate a first digital signal and the overvoltage is compared with a second threshold voltage to generate a second digital signal;

the power management circuitry comprises a digital block receiving the first digital signal and the second digital signal; and

a dither is adjusted in response to the first digital signal.

2. The integrated circuit of claim 1 , wherein the display panel is a liquid-crystal display (“LCD”).

3. The integrated circuit of claim 1 , wherein controlling the power consumption of the panel backlight includes controlling the brightness level of the panel backlight.

4. The integrated circuit of claim 3 , wherein the power management circuitry is configured to control the power consumption of the panel backlight based on user input received by the integrated circuit.

5. The integrated circuit of claim 1 , wherein the digital block turns a digital pulsed-width modulated signal off if the second digital signal indicates an overvoltage.

6. The integrated circuit of claim 1 , further including a third digital signal and a fourth digital signal generated by comparing the feedback voltage with a third threshold and a fourth threshold, respectively.

7. The integrated circuit of claim 6 , wherein the digital block fully controls duration and duty cycle of a digital pulsed-width modulation signal based on the first digital signal, the second digital signal, the third digital signal, and the fourth digital signal.

8. A method of controlling power to a display, comprising:

starting power to a LED array;

checking a low-frequency pulse-width modulation (LPWM) signal and,

on a high condition,

compare a feedback voltage with a first threshold voltage to provide a first digital signal,

compare an overvoltage signal with a second threshold voltage to provide a second digital signal, and

adjust a duty cycle and a dither for a digital pulsed width modulation (DPWM) signal in response to the first digital signal and the second digital signal; and

on a low condition,

setting the DPWM signal to low, and

saving the DPWM duty cycle.

Assignments (4)
SECURITY INTEREST Recorded Sep 27, 2017
From: SYNAPTICS INCORPORATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 044037/0896 →
SECURITY INTEREST Recorded Oct 3, 2014
From: SYNAPTICS INCORPORATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 033888/0851 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2012
From: INTEGRATED DEVICE TECHNOLOGY, INC.
To: SYNAPTICS INCORPORATED
Reel/Frame 028872/0702 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 20, 2009
From: GODER, DIMITRY
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 023552/0687 →
Continuity (2)
Provisional Application 61120811 · Dec 8, 2008
Related Publication 20100141633A1 · Jun 10, 2010