Tiled light sensing array

1. A method of forming a light sensing arrangement for use in a light sensor, the method comprising tiling a plurality of individual light sensing elements side-by-side on a carrier, each element having a notch formed through the element, the notch being adapted to provide space, when the elements are tiled together, for an electrical connection to be made between the carrier and a surface of the element arranged to face away from the carrier.

2. A method as claimed in claim 1 , wherein each element comprises solid-state light sensing circuitry; and/or wherein each element comprises a silicon die; and/or wherein each element comprises Silicon Photomultiplier circuitry; and/or wherein each element comprises high-gain light sensing circuitry, for example having a gain greater than 10 3 or greater than 10 5 .

3. A method as claimed in claim 1 , wherein the element and the space provided by the notch together define a regular shape, such as a rectangular or square shape, and wherein the notch is optionally adapted to provide space for the electrical connection to be made substantially without the electrical connection protruding outside the bounds of the shape.

4. A method as claimed in claim 1 , comprising forming a plurality of unit cells, each unit cell comprising the carrier and plurality of elements tiled on the carrier, and keeping the unit cells for subsequent arrangement into an array of unit cells.

5. A method as claimed in claim 4 , comprising tiling together the plurality of unit cells to form an array of unit cells and/or arranging the elements on the carriers so as to provide minimal dead space between adjacent elements when disposed on different respective unit cells of the array of unit cells.

6. A method as claimed in claim 1 , comprising forming a plurality of die on a wafer, the die forming the respective elements, and removing material from the wafer to form the notches before dicing the wafer.

7. A method as claimed in claim 6 , comprising: removing material by etching, laser ablation, sawing or any other appropriate means; and/or simultaneously forming the notches for a plurality of die by removing material at a boundary between those die; and/or dicing the wafer.

8. A method as claimed in claim 1 , comprising aligning the elements on the carrier by use of alignment features provided on the carrier.

9. A method as claimed in claim 1 , comprising providing first and second contacts on the carrier for each element, the first contact for making the electrical connection through the notch to the surface of the element facing away from the carrier, and the second contact for making a further electrical connection to a surface of the element facing the carrier, and optionally comprising making the further electrical connection by use of conductive adhesive epoxy.

10. A method as claimed in claim 1 , comprising: making the electrical connection through the notch by use of wire bonding; and/or minimising the height and/or distance of travel of the wire bond; and/or arranging adjacent elements on the carrier with minimal dead spacing between them; and/or arranging adjacent elements on the carrier substantially to abut one another; and/or using substantially planar elements; and/or forming a tiled arrangement having an overall active area greater than 1 square cm in area, for example greater than 5 square cm in area and/or greater than 10 square cm in area; and/or arranging electrical connections to enable a separate output from each element; and/or arranging electrical connections to enable a single output for all elements or for a group of elements.

11. A method as claimed in claim 1 , wherein the notch is rectangular shaped; and/or wherein the notch is square shaped; and/or wherein the notch is disposed in a corner of the element; and/or wherein the notch is formed in an edge of the element; and/or; and/or wherein the active area of each element extends substantially to the edges of the element.

12. A method as claimed in claim 1 , comprising forming a plurality of notches, and optionally forming a notch for each electrical connection required to the surface of the element facing away from the carrier.

13. A light sensing element suitable for use in a method as claimed in claim 1 .

14. A unit cell formed by a method as claimed in claim 4 .

15. A wafer formed by a method as claimed in claim 6 .