Pixel structure
A pixel structure having an SMII (semiconductor-metal-insulator-ITO) capacitor is provided. Specifically, a partial region of a transparent electrode layer corresponding to a semiconductor layer is removed, so as to eliminate parasitic capacitance between the transparent electrode layer and the semiconductor layer, prevent defects (e.g., waterfall, image sticking, etc.) from occurring on the display frame, and improve the display quality.
1. A pixel structure comprising:
a substrate;
a scan line configured on the substrate;
a data line configured on the substrate, an extension direction of the data line intersecting an extension direction of the scan line;
a thin film transistor configured on the substrate and electrically connected to the scan line and the data line;
a semiconductor layer configured on the substrate;
a metal capacitor electrode configured on the semiconductor layer, a projection area of the metal capacitor electrode on the substrate being located within a projection area of the semiconductor layer on the substrate, and an edge of the projection area of the metal capacitor electrode being spaced from an edge of a projection area of the semiconductor layer;
a passivation layer configured on the substrate and covering the scan line, the data line, the thin film transistor, the metal capacitor electrode, and the semiconductor layer;
a pixel electrode configured on the passivation layer and electrically connected to the thin film transistor, a projection area of the pixel electrode on the substrate being located outside the projection area of the semiconductor layer on the substrate; and
a transparent capacitor electrode configured on the passivation layer, a projection area of the transparent capacitor electrode on the substrate being located within the projection area of the metal capacitor electrode on the substrate.
2. The pixel structure as claimed in claim 1 , wherein a minimum distance between an edge of the projection area of the transparent capacitor electrode on the substrate and the edge of the projection area of the metal capacitor electrode on the substrate is greater than or substantially equal to 0 micrometer and smaller than or substantially equal to 6 micrometers.
3. The pixel structure as claimed in claim 1 , wherein a minimum distance between an edge of the projection area of the transparent capacitor electrode on the substrate and the edge of the projection area of the metal capacitor electrode on the substrate is greater than or substantially equal to 1 micrometer and smaller than or substantially equal to 4 micrometers.
4. The pixel structure as claimed in claim 1 , wherein a minimum distance between an edge of the projection area of the pixel electrode on the substrate and the edge of the projection area of the semiconductor layer on the substrate is greater than or substantially equal to 1.6 micrometer and smaller than or substantially equal to 6 micrometers.
5. The pixel structure as claimed in claim 1 , wherein a minimum distance between an edge of the projection area of the pixel electrode on the substrate and the edge of the projection area of the semiconductor layer on the substrate is greater than or substantially equal to 2 micrometers and smaller than or substantially equal to 4 micrometers.
6. The pixel structure as claimed in claim 1 , further comprising a gate metal layer located on the substrate, a projection area of the gate metal layer on the substrate at least covering an area of the substrate other than the projection area of the pixel electrode on the substrate.
7. The pixel structure as claimed in claim 6 , further comprising a gate insulation layer configured between the passivation layer and the substrate, the gate insulation layer covering the gate metal layer.
8. The pixel structure as claimed in claim 1 , wherein the pixel electrode has a plurality of fine slits.