Bi-directional driving circuit of liquid crystal display panel
A bi-directional driving circuit of a liquid crystal display (LCD) panel is disclosed, in which forward scanning and backward scanning are available. In a bi-directional driving circuit of an LCD panel having a plurality of blocks, each block includes a first start pulse input terminal to which a start pulse or an output signal of a previous block is input and a second start pulse input terminal to which the start pulse or an output signal of a next block is input. Also, each block includes a first switching portion switching a start pulse signal applied to an input terminal of a first block among the blocks and switching an output signal of a previous block, which is applied to input terminals of the other blocks and a second switching portion switching a start pulse signal applied to an input terminal of the last block and switching an output signal of a previous block, which is applied to input terminals of the other blocks.
1. A bi-directional driving circuit of a liquid crystal display (LCD) panel having a plurality of blocks, each block outputting a signal, the bi-directional driving circuit comprising:
a first switching element having a source and a gate for receiving one of a start pulse and an output signal of a previous block;
a second switching element having a source connected to a drain of the first switching element and a gate for receiving a first clock signal;
a third switching element having a source directly connected to a drain of the second switching element and a drain directly connected to a ground terminal Vss;
a fourth switching element having a source connected to a power source voltage terminal Vdd, a gate connected to a second clock signal, and a drain connected to a gate of the third switching element;
a fifth switching element having a source connected to the drain of the fourth switching element, a gate connected to the drain of the first switching element, and a drain connected to the Vss terminal;
a sixth switching element having a source connected to a third clock signal, a gate connected to the drain of the second switching element, and a drain connected to an output terminal;
a seventh switching element having a source connected to the output terminal, a gate connected to the drain of the fourth switching element, and a drain connected to the Vss terminal;
an eighth switching element having a source and a gate for receiving one of the start pulse and an output terminal of a next block and a drain connected to the drain of the first switching element; and
a ninth switching element connected to the second switching element in parallel, having a gate connected to a third clock signal.