IP Library Granted Patent US 8,426,972
Granted Patent B2
US 8,426,972 · App. 13/345,165 · Granted Apr 23, 2013

Semiconductor device and method for manufacturing the same

Inventor: Keisuke Kimura (Nagoya, JP)
Assignee: Toyota Jidosha Kabushiki Kaisha
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Quick Facts
Patent No.
US 8,426,972
App. No.
13/345,165
Granted
Apr 23, 2013
Kind
B2
Abstract

A semiconductor device has: a semiconductor substrate; and an upper surface electrode laminated on an upper surface of the semiconductor substrate, wherein at least one portion of the upper surface electrode includes a first layer formed on an upper surface side of the semiconductor substrate, a second layer formed on an upper surface side of the first layer, a third layer in contact with the upper surface of the second layer, and a fourth layer formed on an upper surface side of the third layer. The first layer is a barrier metal layer. The second layer is an Al (aluminum) layer. The third layer is one of an Al—Si (aluminum-silicon alloy) layer, an Al—Cu (aluminum-copper alloy) layer and an Al—Si—Cu (aluminum-silicon-copper alloy) layer. The fourth layer is a solder joint layer.

Claims (15)

1. A semiconductor device comprising:

a semiconductor substrate; and

an upper surface electrode laminated on an upper surface of the semiconductor substrate, wherein

at least one portion of the upper surface electrode includes a first layer formed on an upper surface side of the semiconductor substrate, a second layer formed on an upper surface side of the first layer, a third layer in contact with the upper surface of the second layer, and a fourth layer formed on an upper surface side of the third layer,

the first layer is a barrier metal layer;

the second layer is an Al layer;

the third layer is one of an Al—Si layer, an Al—Cu layer and an Al—Si—Cu layer; and

the fourth layer is a solder joint layer.

2. A method for manufacturing a semiconductor device comprising a semiconductor substrate and an upper surface electrode laminated on an upper surface of the semiconductor substrate,

the method comprising:

forming a first layer by a barrier metal on the upper surface of the semiconductor substrate;

forming a second layer by an aluminum on an upper surface of the first layer after forming a first layer;

forming a third layer by one of an Al—Si, an Al—Cu and an Al—Si—Cu on an upper surface of the second layer after forming the second layer;

performing zinc substitution treatment on an upper surface of the third layer after forming the third layer; and

forming a fourth layer, which is a solder joint layer, on the upper surface of the third layer by nonelectrolytic plating after performing zinc substitution treatment.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: TOYOTA JIDOSHA KABUSHIKI KAISHA
To: DENSO CORPORATION
Reel/Frame 052281/0019 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2012
From: KIMURA, KEISUKE
To: TOYOTA JIDOSHA KABUSHIKI KAISHA
Reel/Frame 027494/0780 →
Continuity (2)
Continuation PCTJP2009062448 · Jul 8, 2009
Related Publication 20120104612A1 · May 3, 2012