Methods of fabricating semiconductor devices
Methods of fabricating semiconductor devices are provided including forming a dielectric interlayer on a substrate, the dielectric interlayer defining an opening therein. A metal pattern is formed in the opening. An oxidization process is performed on the metal pattern to form a conductive metal oxide pattern, and the conductive metal oxide pattern is planarized. Related semiconductor devices are also provided.
1. A method of fabricating a semiconductor device, comprising:
forming a dielectric interlayer on a substrate, the dielectric interlayer defining an opening therein;
forming a metal pattern in the opening of the dielectric interlayer;
performing an oxidization process on the metal pattern to form a conductive metal oxide pattern;
planarizing the conductive metal oxide pattern; and
performing a reduction process on the planarized conductive metal oxide pattern.
2. The method of claim 1 , further comprising performing the reduction process in a hydrogen atmosphere.
3. The method of claim 1 , further comprising performing the reduction process in a hydrogen/nitrogen atmosphere.
4. The method of claim 1 , further comprising forming a variable resistor electrically connected to the reduced conductive metal oxide pattern.
5. A method of fabricating a semiconductor device, comprising:
forming a dielectric interlayer on a substrate, the dielectric interlayer defining an opening therein;
forming a metal pattern in the opening of the dielectric interlayer;
performing an oxidization process on the metal pattern to form a conductive metal oxide pattern;
planarizing the conductive metal oxide pattern,
wherein planarizing the conductive metal oxide pattern comprises planarizing an upper portion of the conductive metal oxide pattern and an upper portion of the dielectric interlayer; and
forming a barrier pattern between an inner surface of the opening and the metal pattern,
wherein an upper portion of the barrier pattern is oxidized in the oxidization process; and
wherein at least a portion of the oxidized portion of the barrier pattern is removed in the planarizing of the conductive metal oxide pattern.
6. A method of fabricating a semiconductor device, comprising:
forming a dielectric interlayer on a substrate, the dielectric interlayer defining an opening therein;
forming a metal pattern in the opening of the dielectric interlayer;
performing an oxidization process on the metal pattern to form a conductive metal oxide pattern;
planarizing the conductive metal oxide pattern;
forming a capping dielectric layer on the substrate after the forming of the conductive metal oxide pattern,
wherein the conductive metal oxide pattern comprises a portion protruding outside the opening, and wherein the planarizing of the conductive metal oxide pattern comprises planarizing the protruding portion of the conductive metal oxide pattern and the capping dielectric layer; and
forming a barrier pattern between an inner surface of the opening and the metal pattern,
wherein an upper portion of the barrier pattern is oxidized in the oxidization process; and
wherein at least a portion of the oxidized portion of the barrier pattern is removed in the planarizing of the conductive metal oxide pattern.
7. The method of claim 1 , further comprising planarizing the conductive metal oxide pattern using a chemical mechanical polishing (CMP) process.
8. A method of fabricating a semiconductor device, comprising:
forming a dielectric interlayer on a substrate, the dielectric interlayer defining an opening therein;
forming a metal pattern in the opening of the dielectric interlayer;
performing an oxidization process on the metal pattern to form a conductive metal oxide pattern;
planarizing the conductive metal oxide pattern; and
forming a lower electrode layer on the planarized conductive metal oxide pattern,
wherein the lower electrode layer is in an amorphous state.
9. The method of claim 8 , further comprising performing a partial planarization process on the lower electrode layer, wherein the partial planarization process is performed through a CMP process.
10. A method of fabricating a semiconductor device, comprising:
forming a dielectric interlayer on a substrate, the dielectric interlayer defining an opening therein;
forming a metal pattern in the opening of the dielectric interlayer;
performing an oxidization process on the metal pattern to form a conductive metal oxide pattern;
planarizing the conductive metal oxide pattern; and
forming a variable resistor electrically connected to the planarized conductive metal oxide pattern.
11. The method of claim 10 :
wherein the metal pattern, the planarized conductive metal oxide pattern, and the variable resistor are stacked in a direction perpendicular to a top surface of the substrate; and
wherein at least a portion of the metal pattern, at least a portion of the planarized conductive metal oxide pattern, and at least a portion of the variable resistor overlap with each other in the perpendicular direction.
12. The method of claim 10 , wherein the variable resistor directly contacts a top surface of the planarized conductive metal oxide pattern.
13. The method of claim 10 , further comprising forming a lower electrode layer on the planarized conductive metal oxide pattern before the forming of the variable resistor, wherein the lower electrode layer is in an amorphous state.
14. The method of claim 13 , further comprising performing a partial planarization process on the lower electrode layer before the forming of the variable resistor.