IP Library Granted Patent US 8,451,618
Granted Patent B2
US 8,451,618 · App. 12/914,274 · Granted May 28, 2013

Integrated antennas in wafer level package

Inventors: Josef Boeck (Munich, DE); Rudolf Lachner (Ingolstadt, DE); Maciej Wojnowski (Munich, DE); Thorsten Meyer (Regensburg, DE)
Assignee: Infineon Technologies AG
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Quick Facts
Patent No.
US 8,451,618
App. No.
12/914,274
Granted
May 28, 2013
Kind
B2
Abstract

A semiconductor module having one or more integrated antennas in a single package is provided herein to comprise a bonding interconnect structure having a plurality of individual bonding elements that are confined to a relatively small area of the bottom of a package. In particular, the semiconductor module comprises a bonding interconnect structure configured to connect an integrated package to a printed circuit board (PCB), wherein the integrated antenna structures are located at greater center-to-center distance from the IC device than the three dimensional interconnect structures. Therefore, the bonding interconnect structures are confined to a connection area that causes a part of the package containing the one or more antenna structures to extend beyond the bonding interconnect structure as a cantilevered structure. Such a bonding interconnect structure result in a package that is in contact with a PCB at a relatively small area that supports the load of the package.

Claims (20)

1. A semiconductor module, comprising:

a printed circuit board;

a package comprising an integrated circuit embedded within a package molding compound and one or more integrated antenna structures coupled to the integrated circuit and configured to radiate electromagnetic radiation for wireless transmission or to receive electromagnetic radiation for wireless reception; and

a bonding interconnect structure having one or more three dimensional interconnect structures vertically positioned between the package and the printed circuit board and configured to physically connect the package to the printed circuit board;

wherein the at least one of the one or more integrated antenna structures is located at a greater center-to-center distance from IC device than the three dimensional interconnect structures.

2. The module of claim 1 , wherein the three dimensional interconnect structures comprise surface-mountable solder balls.

3. The module of claim 1 , wherein the bonding interconnect structure is configured to physically connect the package to the printed circuit board at a position that supports the package as a cantilevered structure that comprises at least part of the one or more integrated antenna structures.

4. The module of claim 1 , further comprising one or more support structures physically coupled to the package and having no electrical connection between the printed circuit board and the package, wherein the support structures are located at greater center-to-center distance from the IC device than the three dimensional interconnect structures.

5. The module of claim 1 , wherein outer edges of the bonding interconnect structure are positioned along a square having an area that is less than 40% of the total area of a bottom surface of the package.

6. The module of claim 1 , wherein the one or more integrated antenna structures comprise a plurality of antenna structures respectively arranged on different sides of the IC device.

7. The module of claim 1 , wherein the one or more integrated antenna structures comprise a plurality of antenna structures separated spatially by an electrically isolating shield layer.

8. The module of claim 1 , wherein the package is formed using a wafer level packaging process and wherein the package comprises a non-rectangular shape that is formed by laser dicing.

9. The module of claim 1 , wherein at least one of the one or more integrated antenna structures is located at a distance from a center of the integrated circuit having a horizontal component that is larger than a horizontal component of a distance from the center of the integrated circuit to the one or more three dimensional interconnect structures.

10. The module of claim 4 , wherein the one or more support structures comprise one or more solder balls coupled to the package.

11. The module of claim 7 , wherein the electrically isolating shield layer comprises a redistribution layer electrically connected to a ground terminal.

12. A semiconductor module, comprising:

a printed circuit board;

a package comprising an integrated circuit and one or more antenna structures laterally disposed from the integrated circuit within the package; and

a bonding interconnect structure comprising a plurality of interconnect structures configured to physically connect the package to the printed circuit board, wherein the plurality of interconnect structures are vertically positioned between the package and the printed circuit board, and wherein the plurality of interconnect structures define a connection area;

wherein the one or more antenna structures are laterally disposed from and do not vertically overlie the connection area.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 28, 2010
From: BOECK, JOSEF; LACHNER, RUDOLF; WOJNOWSKI, MACIEJ; MEYER, THORSTEN
To: INFINEON TECHNOLOGIES AG
Reel/Frame 025211/0642 →
Continuity (1)
Related Publication 20120104574A1 · May 3, 2012