Silicide formation and associated devices
View Patent ↗Improved silicide formation and associated devices are disclosed. An exemplary method includes providing a semiconductor material having spaced source and drain regions therein, forming a gate structure interposed between the source and drain regions, performing a gate replacement process on the gate structure to form a metal gate electrode therein, forming a hard mask layer over the metal gate electrode, forming silicide layers on the respective source and drain regions in the semiconductor material, removing the hard mask layer to expose the metal gate electrode, and forming source and drain contacts, each source and drain contact being conductively coupled to a respective one of the silicide layers.
1. A method comprising:
providing a semiconductor substrate;
forming a fin structure extending upwardly from the substrate, the fin structure having spaced source and drain regions therein;
forming a gate structure engaging the fin structure between the source and drain regions, the gate structure having a dummy gate electrode therein;
depositing a first inter-level dielectric (ILD) layer over the gate structure and fin structure;
removing the dummy gate electrode to form a trench in the gate structure;
depositing a metal layer into the trench to form a metal gate electrode therein;
removing a top portion of the metal gate electrode to form an opening in the gate structure;
forming a hard mask layer in the opening;
removing the first ILD layer to expose the source and drain regions in the fin structure;
forming silicide layers on the respective source and drain regions in the fin structure;
removing the hard mask layer; and
forming source and drain contacts, each source and drain contact being conductively coupled to a respective one of the silicide layers.
2. The method of claim 1 , further including:
depositing a second ILD layer over the silicide layers and the hard mask layer; and
performing a chemical-mechanical polishing (CMP) process to planarize the second ILD layer.
3. The method of claim 2 , wherein the performing the CMP process includes the removing the hard mask layer.
4. The method of claim 1 , wherein the removing the top portion of the metal gate electrode includes removing a portion of the metal gate electrode having a thickness in the range of approximately 5 to 10 nanometers.
5. The method of claim 1 , including forming epitaxial growths in the source and drain regions after forming the gate structure.
6. The method of claim 1 , wherein forming the gate structure includes forming spacers on sidewalls of the gate structure, the spacers partially defining the opening after the removing the top portion of the metal gate electrode.
7. The method of claim 6 , wherein the removing the hard mask layer includes removing portions of the spacers surrounding the hard mask layer.
8. The method of claim 1 , wherein the forming the silicide layers includes forming the silicide layers such that they extend outwardly from the gate structure along approximately the entirety of each of the respective source and drain regions.
9. A method comprising:
providing a semiconductor substrate;
forming a fin structure extending upwardly from the substrate;
forming a gate structure engaging the fin structure, the gate structure having a dummy gate electrode therein;
depositing a first inter-level dielectric (ILD) layer over the gate structure and fin structure;
removing the dummy gate electrode to form a trench in the gate structure;
depositing a metal layer into the trench to form a metal gate electrode therein;
removing a top portion of the metal gate electrode to form an opening in the gate structure;
forming a hard mask layer in the opening;
removing the first ILD layer to expose source and drain regions;
forming silicide layers on the respective source and drain regions;
removing the hard mask layer; and
forming source and drain contacts, each source and drain contact being conductively coupled to a respective one of the silicide layers.