Nonvolatile memory device, operating method thereof and memory system including the same
A method of operating a non-volatile memory device includes storing one or more addresses of word lines (WLs), but not the entire addresses of the WLs, into a latch, the WLs disposed between a string selection line (SSL) and a ground selection line (GSL), selecting a first WL from the latch, performing an erasing operation on memory cells associated with the string selection line (SSL), the memory cells associated with the SSL constituting a memory block, and verifying the erasing operation on memory cells associated with the selected first WL.
1. A method of operating a non-volatile memory device, the method comprising:
storing into a latch one or more, but not all, addresses of word lines (WLs) disposed between a string selection line (SSL) and a ground selection line (GSL);
performing an erasing operation on memory cells associated with the string selection line (SSL), the memory cells associated with the SSL constituting a memory block; and
verifying the erasing operation on memory cells associated with the WLs corresponding to the stored addresses, wherein performing the erasing operation and verifying the erasing operation are repeated at least two times, and wherein at least one of the WLs, which is verify-passed during a verifying step, is not verified during a next verifying step.
2. The method of claim 1 , further comprising:
resetting an erase count prior to the erasing operation.
3. The method of claim 2 ,
wherein verifying the erasing operation comprises:
selecting a first WL from the latch to verify memory cells associated with the selected first WL; and
selecting a second WL from the latch to verify memory cells associated with the selected second WL when the memory cells associated with the first WL are verify-passed.
4. The method of claim 3 , further comprising:
counting up the erase count when the memory cells associated with the first WL are verify-failed; and
adjusting an erase voltage to erase the memory block.
5. The method of claim 2 , further comprising:
deleting the address of the first WL when the memory cells associated with the first WL are verify-passed; and selecting a second WL from the latch.
6. The method of claim 5 , further comprising:
selecting a second WL from the latch when the memory cells associated with the first WL are verify-failed.
7. The method of claim 6 , further comprising:
counting up the erase count when the latch stores any WL address after verifying the last stored WL address.
8. The method of claim 4 , further comprising:
performing an error report when the erase count reaches a preset value.
9. The method of claim 1 , wherein the memory block includes a plurality of NAND strings connected to one bit line.
10. The method of claim 1 , wherein the one or more addresses of the word lines (WLs) correspond to a word line connected to memory cells having slower erase speed as compared to memory cells connected to a word line whose address is not stored in the latch, or correspond to a word line located at an edge among the word lines.
11. The method of claim 1 , wherein the address of the first WL stored in the latch is received from a fuse in a fuse unit.
12. A non-volatile memory device comprising:
a memory cell array comprising memory cells associated with a string selection line (SSL);
a voltage generating unit configured to generate an erase voltage for performing an erasing operation on the memory cells associated with the string selection line (SSL), the memory cells associated with the SSL constituting a memory block; and
a control logic comprising a latch configured to store one or more addresses of word lines (WLs), but not the entire addresses of the WLs, into the latch, the WLs disposed between an SSL and a GSL,
wherein the control logic is configured to perform the erasing operation and verify the erasing operation based on the stored addresses iteratively, and wherein at least one of the WLs, which is verify-passed during a verifying step, is not verified during a next verifying step.
13. The non-volatile memory device of claim 12 , wherein the address of the first WL is received from a fuse in a fuse unit.
14. The non-volatile memory device of claim 12 , further comprising:
an address decoder connected to the memory cell array through SSLs, word lines, and at least one ground selection line (GSL).
15. The non-volatile memory device of claim 12 , further comprising:
a read/write circuit connected to the memory cell array through bit lines.
16. The non-volatile memory device of claim 12 , further comprising:
a pass/fail check unit for determining whether the verification of the erasing operation has failed or passed.
17. The non-volatile memory device of claim 16 , wherein the control logic further comprises an erase control unit and an erase counter, the erase control unit receiving pass/fail data from the pass/fail check unit.
18. The non-volatile memory device of claim 12 , wherein the non-volatile memory device is configured to receive a signal from a controller.
19. The non-volatile memory device of claim 18 , wherein the controller includes a RAM, a processing unit, a host interface, and a memory interface.
20. The non-volatile memory device of claim 12 , wherein the non-volatile memory device is configured to perform an error report if performing the erasing operation and verifying the erasing operation are repeated a predetermined number of times.
21. A method of operating a non-volatile memory device, the method comprising:
storing into a latch one or more, but not all, addresses of word lines (WLs disposed between an SSL and a GSL;
performing an erasing operation on memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block; and
verifying the erasing operation on memory cells associated with the WLs corresponding to the stored addresses and a selected SSL among the SSLs,
wherein performing the erasing operation and verifying the erasing operation are repeated at least two times, and wherein at least one of the WLs, which is verify-passed during a verifying step, is not verified during a next verifying step.
22. The method of claim 21 , further comprising:
resetting an SSL count and an erase count prior to the erasing operation.
23. The method of claim 22 , further comprising:
counting up the SSL count when memory cells associated with the first SSL are verify passed, wherein an SSL is selected among the SSLs according to the SSL count.
24. The method of claim 23 , further comprising:
counting up the erase count when the memory cells associated with the first WL are verify-failed; and
adjusting an erase voltage to erase the memory block.
25. The method of claim 23 , further comprising:
selecting a second WL from the latch when the memory cells associated with the first WL are verifying-passed.
26. The method of claim 23 , further comprising:
deleting the address of the first WL when the memory cells associated with the first WL are verify-passed; and selecting a second WL from the latch.
27. The method of claim 26 , further comprising:
selecting a second WL from the latch when the memory cells associated with the first WL are verify-failed.
28. The method of claim 27 , further comprising:
counting up the erase count when the latch stores any WL address after verifying the last stored WL address.
29. The method of claim 28 , further comprising:
performing an error report when the erase count reaches a preset value.
30. The method of claim 21 , wherein the memory cells of the non-volatile memory device are stacked in a direction perpendicular with respect to a major axis of a substrate where the memory cells are disposed.