Electrostatic discharge protection device and method for fabricating the same
The present invention provides an ESD protection device comprising a SCR structure that is a transverse PNPN structure formed by performing a P-type implantation and an N-type implantation in an N-well and a P-well on a silicon substrate, respectively, wherein a P-type doped region in the N-well is used as an anode, and N-type doped region in the P-well is used as a cathode, characterized in that, N-type dopants are implanted into the N-well to form one lead-out terminal of a resistor, P-type dopants are implanted into the P-well to form another lead-out terminal for the resistor, and the two leading-out terminals are connected by the resistor.
1. An ESD protection device comprising an SCR structure which is a transverse PNPN structure formed by performing a P-type implantation and an N-type implantation into an N-well and a P-well on a silicon substrate, respectively, wherein a P-type doped region in the N-well is used as an anode, and an N-type doped region in the P-well is used as a cathode, characterized in that, N-type dopants are implanted into the N-well to form one lead-out terminal of a resistor, P-type dopants are implanted into the P-well to form another lead-out terminal of the resistor, and the two lead-out terminals are connected through the resistor.
2. The device according to claim 1 , characterized in that, the resistor is a polysilicon resistor or an active region resistor.
3. The device according to claim 1 , characterized in that, the N-well and the P-well on the silicon substrate are isolated by STI.
4. A method for fabricating an ESD protection device, comprising steps of:
1) performing a P-type implantation and an N-type implantation on a silicon substrate to form an N-well and a P-well, respectively;
2) etching the polysilicon to form a resistor when forming a polysilicon gate structure;
3) performing a heavy N-type doping implantation on a region of a part of the N-well to form an N+ region to be used as one lead-out terminal of the resistor, while performing a heavy N-type doping implantation on a region of a part of the P-well to form a cathode of the device;
4) performing a heavy P-type doping implantation on a region of a part of the P-well to form a P+ region to be used as another lead-out terminal for the resistor, while performing a heavy P-type doping implantation on a region of a part of the N-well to form an anode of the device;
5) using a standard process for CMOS to finish subsequent fabrication of the ESD protection device.
5. The method according to claim 4 , characterized in that, in the step 1), concentrations for the P-type implantation and the N-type implantation are 1017 to 1018/cm3.
6. The method according to claim 4 , characterized in that, in the step 3) and step 4), concentrations for the heavy P-type doping implantation and the heavy N-type doping implantation are 1019 to 1021/cm3.
7. The method according to claim 4 , characterized in that, in the step 1), the N-well and the P-well on the silicon substrate are isolated by STI.