Semiconductor memory device including ferroelectric capacitor
An aspect of the present disclosure, there is provided semiconductor memory device including a ferroelectric capacitor and a field effect transistor as a memory cell, the ferroelectric capacitor including a lower electrode connected to one of the pair of the impurity diffusion layers, a bit line formed below the lower electrode, wherein each of the memory cells shares the bit line contact with an adjacent memory cell at one side in the first direction to connect to the bit line, and three of the word lines are formed between the bit line contacts in the first direction.
1. A semiconductor memory device comprising a ferroelectric capacitor comprising:
a substrate;
a field effect transistor comprising a word line on the substrate via an insulating layer and a pair of impurity diffusion layers in an element region in a surface layer of the substrate, the word line being interposed between the pair of impurity diffusion layers;
a ferroelectric capacitor above the substrate, the ferroelectric capacitor comprising a lower electrode connected to a first one of the pair of the impurity diffusion layers, a ferroelectric film on the lower electrode, and an upper electrode on the ferroelectric film; and
a bit line below the lower electrode, the bit line connecting to a second one of the pair of impurity diffusion layers via a bit line contact;
wherein each of memory cells comprises the field effect transistor and the ferroelectric capacitor, a memory cell group comprises the memory cells in a first direction with a predetermined pitch, and memory cells in the group are aligned in rows in a second direction,
each memory cell is configured to share the bit line contact with an adjacent memory cell at one side in the first direction and to connect to the bit line, and
three of the word lines are disposed between the bit line contacts in the first direction; and
wherein the bit line is at an acute angle to the first direction, and the ferroelectric capacitor is substantially perpendicular to the word line.
2. The semiconductor memory device of claim 1 , wherein
the memory cells are at an acute angle to a direction in parallel to the bit line.
3. The semiconductor memory device of claim 2 , wherein
the element region comprises a first portion perpendicular to the word line, and a second portion continuous to the first portion and extending in parallel to the word line.
4. The semiconductor memory device of claim 1 , wherein
sizes of the ferroelectric capacitor are twice as much as the minimum processing size in the first direction and 1.83 times as much as the minimum processing size in the second direction.
5. The semiconductor memory device of claim 1 , wherein
a width of the bit line is smaller than the minimum processing size.
6. The semiconductor memory device of claim 5 , wherein
sizes of the ferroelectric capacitor are twice as much as the minimum processing size in the first direction and 1.66 times as much as the minimum processing size in the second direction.
7. The semiconductor memory device of claim 1 , wherein
the memory cell in the first direction is formed shifted by a predetermined distance in the first direction with respect to an adjacent memory cell in the second direction.
8. The semiconductor memory device of claim 7 , wherein
a distance of the shift amount is half of the predetermined distance.
9. The semiconductor memory device of claim 1 , wherein
the lower electrode comprises iridium.
10. The semiconductor memory device of claim 1 , wherein
the ferroelectric film comprises PZT or SBT.
11. The semiconductor memory device of claim 1 , wherein
the upper electrode comprises iridium, iridium oxide, or platinum.