Satellite communication system utilizing low density parity check codes
An approach for reliably communicating over a satellite in support of a communication service including, for example, as direct broadcast satellite and data service, is disclosed. An input message is encoded, yielding a structured Low Density Parity Check (LDPC) coded message. The coded message is modulated according to a high order modulation scheme that has a signal constellation representing more than two symbols per signaling point—e.g., 8-PSK (Phase Shift Keying) and 16-QAM (Quadrature Amplitude Modulation). The system includes a transmitter configured to propagate the modulated signal over the satellite. The above approach is particularly applicable to bandwidth constrained communication systems requiring high data rates.
1. A method comprising:
receiving a block of k data bits;
encoding the block of data bits using Low Density Parity Check (LDPC) code having a corresponding parity check matrix of the form [A (n-k)xk B (n-k)x(n-k) ] wherein n represents a length of the LDPC code, wherein the submatrix B is lower triangular and wherein the LDPC code is configured to enable structured access to edge values in a decoding process; and
generating a radio communications signal from the encoded block of data bits.
2. The method of claim 1 , wherein the LDPC code is configured to enable simultaneous retrieval of relevant edge values corresponding to a group of bit nodes or a group of check nodes from a memory in the decoding process.
3. The method of claim 1 , wherein the decoding process is a partially parallel decoding process.
4. The method of claim 1 , wherein the LDPC code is configured to enable non-random storage of edge values in the decoding process.
5. The method of claim 1 , wherein the LDPC code is cycle -4 and cycle-6 free.
6. An apparatus comprising:
an encoding circuit configured to a block of k data bits and to encode the block of data bits using a Low Density Parity Check (LDPC) code having a corresponding parity clock matrix of the form [A (n-k)xk B (n-k)x(n-k) ] wherein n represents a length of the LDPC code, wherein the submatrix B is lower triangular and wherein the LDPC code is configured to enable structured access to edge value in a decoding process.
7. The apparatus of claim 6 , wherein the LDPC code is configured to enable simultaneous retrieval of relevant edge values corresponding to a group of bit nodes or a group of check nodes from a memory in the decoding process.
8. The apparatus of claim 6 , wherein the decoding process is a partially parallel decoding process.
9. The apparatus of claim 6 , wherein the LDPC code is configured to enable non-random storage of edge values in the decoding process.
10. The apparatus of claim 6 , wherein the LDPC code is cycle-4 and cycle-6 free.
11. The apparatus of claim 6 , further comprising a radio communications circuit configured to generate a radio signal from the encoded block of data bits.
12. An apparatus comprising:
a radio communications circuit configured to receive a radio communications signal; and
a decoder circuit configured to decode the received radio communications signal according to a Low Density Parity Check (LDPC) code to recover an encoded block of k data bits therein, wherein the LDPC code has a corresponding parity check matrix of the form [A (n-k)xk B (n-k)x(n-k) ] wherein n represents a length of the LDPC code, wherein the submatrix B is lower triangular and wherein the LDPC code is configured to enable structured access to edge values in a decoding process.
13. The apparatus of claim 12 , wherein the LDPC code is configured to enable simultaneous retrieval of relevant edge values corresponding to a group of bit nodes or a group of check nodes from a memory in the decoding process.
14. The apparatus of claim 12 , wherein the decoding process is a partially parallel decoding process.
15. The apparatus of claim 12 , wherein the LDPC code is configured to enable non-random storage of edge values in the decoding process.
16. The apparatus of claim 12 , wherein the LDPC code is cycle-4 and cycle-6 free.
17. A method comprising:
receiving a radio communications signal; and
decoding the received radio communications signal according to a Low Density Parity Check (LDPC) code to an encoded block of k data bits therein, wherein the LDPC code has a corresponding parity check matrix of the form [A (n-k)xk B (n-k)x(n-k) ] wherein n represents a length of the LDPC code, wherein the submatrix B is lower triangular and wherein the LDPC code is configured to enable structured access to edge values in a decoding process.
18. The method of claim 17 , wherein the LDPC code is configured to enable simultaneous retrieval of relevant edge values corresponding to a group of bit nodes or a group of check nodes from a memory in the decoding process.
19. The method of claim 17 , wherein the decoding process is a partially parallel decoding process.
20. The method of claim 17 , wherein the LDPC code is configured to enable non-random storage of edge values decoding process.
21. The method of claim 17 , wherein the LDPC code is cycle-4 and cycle-6 free.