Current protection circuit for intelligent power switch

1. An intelligent power switch (IPS) circuit providing current protection for a power switch, a gate terminal of the power switch being controlled by a first control signal generated by a gate driver, the circuit comprising:

a first circuit to measure a current in the power switch, determine a first difference between a first voltage and a first reference voltage, and reduce the first control signal if the first difference exceeds a first predetermined limit; and

a second circuit distinct from the first circuit, the second circuit to measure the current in the power switch and determine a second difference between the first voltage and a second reference voltage, wherein if the second difference exceeds a second predetermined limit the first control signal is set to turn OFF the power switch;

said power switch configured such that a desirable value of said current is less than or equal to 50 amperes.

2. The circuit of claim 1 , wherein the second reference voltage is above the first reference voltage.

3. The circuit of claim 1 , wherein the power switch is turned OFF in at least one case selected from overcurrent, overtemperature, and other overloads.

4. The circuit of claim 1 , wherein the first circuit further comprises a first current measuring circuit to measure the current in the power switch, the first current measuring circuit being selected from at least one of a first switch parallel connected to the power switch, an external shunt in series with the power switch, a resistor in series with the power switch.

5. The circuit of claim 4 , wherein the first current measuring circuit includes the first switch parallel connected to the power switch and the resistor in series with the power switch, wherein, the first switch passes a small fraction of a current flowing through the power switch and the resistor is connected between a source terminal of the first switch and a source terminal of the power switch for sensing the current and determining the amount of current going to a load.

6. The circuit of claim 5 , wherein the load is selected from at least one of resistive and reactive components.

7. The circuit of claim 4 , wherein the first current measuring circuit is selected from at least one of components integral with and separate from the power switch.

8. The circuit of claim 4 , wherein the second circuit further comprises a second current measuring circuit to measure the current in the power switch, the second current measuring circuit being a second switch having a terminal connected to the gate terminal of the power switch and a second terminal connected to a main terminal of the power switch, wherein when the second switch is turned ON the power switch turns OFF.

9. The circuit of claim 8 , wherein the first circuit further comprises a first comparator to determine the first difference and the second circuit further comprises a second comparator to determine the second difference.

10. The circuit of claim 9 , wherein the second circuit further comprises a setting device connected to the second comparator to receive control signals and to a gate of the second switch, wherein after receiving a SET control signal from the second comparator the latch turns ON the second switch thereby turning OFF the power switch.

11. The circuit of claim 10 , wherein the setting device is selected from at least one of a latch having a reset input, a monostable, and a one-shot.

12. The circuit of claim 10 , wherein a slow turn ON and turn OFF of the power switch in normal operation ensure low electromagnetic interference (EMI) generation.

13. An intelligent power switch (IPS) circuit to control a gate terminal of a power switch, the IPS circuit comprising:

a first circuit to monitor a monitored current passing through the power switch, the first circuit configured to control/reduce/terminate a gate current to the power switch if the monitored current is excessive;

a second circuit distinct from the first circuit, the second circuit to monitor the monitored current, the second circuit configured to implement a predetermined delay in a turn OFF of the power switch;

wherein the first circuit and the second circuit measure a first voltage across a resistor parallel connected with the power switch to monitor said monitored current.

14. The IPS circuit of claim 13 , wherein the second circuit comprises a setting device.

15. The IPS circuit of claim 14 , wherein the setting device comprises one of a latch having a reset input, a monostable, and a one-shot.

16. The IPS circuit of claim 13 , wherein the second circuit is configured to ensure a low electromagnetic interference (EMI) during a normal operation of the IPS circuit.

17. The IPS circuit of claim 13 , wherein the IPS circuit is adapted for use with a motor.

18. The IPS circuit of claim 13 , wherein:

the first circuit comprises a comparator configured to control/reduce/terminate the gate current based on the first voltage.

19. The IPS circuit of claim 13 , wherein:

the second circuit comprises a comparator configured to implement the predetermined delay based on the first voltage.

20. The IPS circuit of claim 13 , wherein the first circuit does not comprise a bipolar junction transistor (BJT).