Array substrate, manufacturing method thereof and liquid crystal display

1. A manufacturing method of an array substrate, comprising:

forming gate lines, data lines, pixel electrodes, and gate electrodes, active layer members, source electrodes, drain electrodes of thin film transistors (TFTs) in pixel units in a display region and farming the gate lines and the data lines in a pad region, wherein a process of forming the data lines, the active layer members, the source electrodes and the drain electrodes in the display region and simultaneously forming the data lines in the pad region comprises:

sequentially forming an active layer film and a data line metal film;

applying a photoresist layer on the data line metal film, and then exposing and developing the photoresist layer to form a first photoresist completely-remained region, a first photoresist partially-remained region and a first photoresist completely-removed region of the photoresist layer;

performing a first wet etching process to etch away the data line metal film in the first photoresist completely-removed region and performing a first dry etching process to etch away the active layer film in the first photoresist completely-removed region, so that the data lines, the source electrodes and the drain electrodes are formed in the pixel units;

ashing to remove the photoresist layer by a thickness of the photoresist in the first photoresist partially-remained region;

performing a second wet etching process to etch away the data line metal film in the first photoresist partially-remained region and performing a second dry etching process to etch away a portion of the active layer film in the first photoresist partially-remained region, so that channel regions of the active layer members are defined in the pixel units and the data lines is formed in the pad region;

ashing to remove the remaining photoresist layer; and

etching away the remaining active layer film in the first photoresist partially-remained region in the pad region.

2. The method according to claim 1 , wherein the process of etching away the remaining active layer film in the first photoresist partially-remained region in the pad region comprises:

forming a passivation layer in the display region and the pad region; and

performing a patterning process with a single-tone mask plate, so that the passivation layer above the drain electrodes is etched away to form passivation layer via holes, and the passivation layer and the remaining active layer film in the first photoresist partially-remained region in the pad region are simultaneously etched away.

3. The method according to claim 1 , wherein the process of etching away the remaining active layer film in the first photoresist partially-remained region in the pad region comprises:

forming a passivation layer in the display region and the pad region; and

performing a patterning process with a dual-tone or half-tone mask plate, so that the passivation layer above the drain electrode is etched away by a first etching process to form passivation layer via holes, and the passivation layer and the remaining active layer film in the first photoresist partially-remained region in the pad region are etched away by a second etching process.

4. The method according to claim 1 , wherein the process of etching away the remaining active layer film in the first photoresist partially-remained region in the pad region comprises:

forming a passivation layer in the display region and the pad region; and

performing a patterning process with a dual-tone or half-tone mask plate, so that a portion of films in the first photoresist partially-remained region in the pad region is etched away by a first etching process, the passivation layer above the drain electrode is etched away by a second etching process to form passivation layer via holes, and the remaining passivation layer and the remaining active layer film in the first photoresist partially-remained region in the pad region is simultaneously etched away by the second etching process.

5. The method according to claim 1 , wherein the data lines are formed of a low-resistivity material.

6. The method according to claim 5 , wherein the low-resistivity material comprises a composite layer of Al and Nd, Al or Cu.

7. The method according to claim 1 , wherein a distance between the data lines in the pad region is smaller than 9 μm.

8. The method according to claim 7 , wherein the distance between the data lines in the pad region is 5 μm.

9. The method according to claim 1 , wherein the active layer film is formed by a plasma enhanced chemical vapor deposition method.

10. The method according to claim 1 , wherein the data line metal film is formed by a magnetron sputtering method.

11. The method according to claim 1 , wherein in the pad region, a gate insulating layer is further formed between the gate lines and the data lines, and a pattern of the gate insulating layer corresponds to that of the data lines.

12. An array substrate, comprising:

a display region comprising gate lines, data lines, pixel electrodes, and gate electrodes, active layer members, source electrodes, and drain electrodes of thin film transistors (TFTs) in pixel units; and

a pad region comprising the gate lines and the data lines extending from the display region into the pad region,

wherein in the pad region, the data lines are formed on an active layer film for forming the active layer members, and a difference between a width of the data lines and that of the underlying active layer film is smaller than a line width difference caused by two wet etching processes.

13. The array substrate according to claim 12 , wherein in the pad region, a gate insulating layer is further formed between the gate lines and the data lines, and a pattern of the gate insulating layer corresponds to that of the data lines.

14. The array substrate according to claim 12 , wherein a distance between the data lines in the pad region is smaller than 9 μm.

15. The array substrate according to claim 14 , wherein the distance between the data lines in the pad region is 5 μm.

16. The array substrate according to claim 12 , wherein the data lines are formed of a low-resistivity material.

17. The array substrate according to claim 16 , wherein the low-resistivity material comprises a composite layer of Al and Nd, Al or Cu.

18. A liquid crystal display comprising a liquid crystal panel, wherein the liquid crystal panel comprises:

a color filter substrate,

an array substrate according to claim 12 , and

a liquid crystal layer sandwiched between the color filter substrate and the array substrate.