Inverter circuit having relatively higher efficiency
The configurations of an inverter circuit are provided in the present invention. The proposed circuit includes a first bridge arm having a first sub-bridge arm with a first switch and a first middle point coupled to the first switch, and a second sub-bridge arm with a second switch and a second middle point coupled to the second switch, a first inductor having a first terminal coupled to the first middle point and a second terminal, and a second inductor having a first terminal coupled to the second middle point, and a second terminal coupled to the second terminal of the first inductor and outputting an AC voltage.
1. An inverter circuit, comprising:
a first bridge arm having:
a first sub-bridge arm having a first switch, a first diode, and a first middle point coupled to the first switch and the first diode; and
a second sub-bridge arm having a second switch, a second diode; and a second middle point coupled to the second switch and the second diode;
a first inductor having a first terminal coupled to the first middle point, and a second terminal; and
a second inductor having a first terminal coupled to the second middle point, and a second terminal coupled to the second terminal of the first inductor and outputting an AC voltage.
2. A circuit according to claim 1 further comprising a second bridge arm having a third and a fourth switches and a third middle point, wherein the third and the fourth switches are coupled to the third middle point, and the third middle point outputs the AC voltage.
3. A circuit according to claim 2 further comprising a first and a second input terminals, wherein each of the first to the fourth switches has a first, a second and a control terminals, each of the first and the second diodes has an anode and a cathode, the second terminal of the first switch and the cathode of the first diode are coupled to the first middle point, the first terminal of the second switch and the anode of the second diode are coupled to the second middle point, the first terminal of the third switch and the second terminal of the fourth switch are coupled to the third middle point, the first terminal of the first switch, the first terminal of the fourth switch and the cathode of the second diode are coupled to the first input terminal, and the second terminal of the second switch, the second terminal of the third switch and the anode of the first diode are coupled to the second input terminal.
4. A circuit according to claim 3 , wherein the first and the second input terminals receive a DC voltage.
5. A circuit according to claim 4 , wherein the DC voltage is an output voltage of a solar cell.
6. A circuit according to claim 3 further comprises a regulator receiving a first DC voltage and generating a second DC voltage, wherein the first and the second input terminals receive the second DC voltage.
7. A circuit according to claim 6 , wherein the first DC voltage is an output voltage of a solar cell.
8. A circuit according to claim 2 , wherein each of the first to the fourth switches is a MOSFET.
9. A circuit according to claim 2 , wherein each of the first and the second switches is a CoolMOS device, and each of the third and the fourth switches is an ordinary MOSFET.
10. A circuit according to claim 2 further comprising a third inductor having a first terminal coupled to the second terminal of the second inductor and a second terminal outputting the AC voltage, wherein each of the first to the third inductors has an inductance, the inductance of the third inductor is larger than both of the respective inductances of the first and the second inductors, the first and the second switches have a first and a second body diodes respectively, the inductance of the first inductor has a lower limit set to prevent from a turn-on of the second body diode when the first switch is turned off and the inductance of the second inductor has a lower limit set to prevent from a turn-on of the first body diode when the second switch is turned off.
11. A circuit according to claim 2 , wherein the first switch is used as a first PWM switch, the first diode provides a first follow current when the first switch is turned off, and the third switch is turned on constantly while the AC voltage is in a positive half-cycle, the second switch is used as a second PWM switch, the second diode provides a second follow current when the second switch is turned off, and the fourth switch is turned on constantly while the AC voltage is in a negative half-cycle.
12. An inverter circuit, comprising:
a first bridge arm having:
a first sub-bridge arm having a first switch, and a first middle point coupled to the first switch; and
a second sub-bridge arm having a second switch, and a second middle point coupled to the second switch;
a first inductor having a first terminal coupled to the first middle point, and a second terminal; and
a second inductor having a first terminal coupled to the second middle point, and a second terminal coupled to the second terminal of the first inductor and outputting an AC voltage.
13. A circuit according to claim 12 further comprising a second bridge arm having a third and a fourth switches and a third middle point, wherein the third and the fourth switches are coupled to the third middle point, the third middle point outputs the AC voltage, the first sub-bridge arm further comprises a first diode coupled to the first middle point, and the second sub-bridge arm further comprises a second diode coupled to the second middle point.
14. A circuit according to claim 13 further comprising a first and a second input terminals, wherein each of the first to the fourth switches has a first, a second and a control terminals, each of the first and the second diodes has an anode and a cathode, the second terminal of the first switch and the cathode of the first diode are coupled to the first middle point, the first terminal of the second switch and the anode of the second diode are coupled to the second middle point, the first terminal of the third switch and the second terminal of the fourth switch are coupled to the third middle point, the first terminal of the first switch, the first terminal of the fourth switch and the cathode of the second diode are coupled to the first input terminal, the second terminal of the second switch, the second terminal of the third switch and the anode of the first diode are coupled to the second input terminal, and the first and the second input terminals receive a DC voltage.
15. An inverter circuit, comprising:
a first bridge arm having:
a first sub-bridge arm having:
a first switch;
a first middle point coupled to the first switch; and
a first diode coupled to the first middle point; and
a second sub-bridge arm having:
a second switch;
a second middle point coupled to the second switch; and
a second diode coupled to the second middle point;
a first inductor having a first terminal coupled to the first middle point, and a second terminal;
a second inductor having a first terminal coupled to the second middle point, and a second terminal coupled to the second terminal of the first inductor; and
a third inductor having a first terminal coupled to the second terminal of the second inductor, and a second terminal outputting an AC voltage.
16. A circuit according to claim 15 further comprising a second bridge arm having a third and a fourth switches and a third middle point, wherein the third and the fourth switches are coupled to the third middle point, and the third middle point is also used for outputting the AC voltage.
17. A circuit according to claim 16 further comprising a first and a second input terminals, wherein each of the first to the fourth switches has a first, a second and a control terminals, each of the first and the second diodes has an anode and a cathode, the second terminal of the first switch and the cathode of the first diode are coupled to the first middle point, the first terminal of the second switch and the anode of the second diode are coupled to the second middle point, the first terminal of the third switch and the second terminal of the fourth switch are coupled to the third middle point, the first terminal of the first switch, the first terminal of the fourth switch and the cathode of the second diode are coupled to the first input terminal, the second terminal of the second switch, the second terminal of the third switch and the anode of the first diode are coupled to the second input terminal, and the first and the second input terminals receive a DC voltage.
18. A circuit according to claim 15 , wherein each of the first to the third inductors has an inductance, the inductance of the third inductor is larger than both of the respective inductances of the first and the second inductors, the first and the second switches have a first and a second body diodes respectively, the inductance of the first inductor has a lower limit set to prevent from a turn-on of the second body diode when the first switch is turned off and the inductance of the second inductor has a lower limit set to prevent from a turn-on of the first body diode when the second switch is turned off.